Shinji Kimura

ORCID

Publication Activity (10 Years)

Years Active: 1982-2024
Publications (10 Years): 46

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

ISCAS

SOCC

ASP-DAC

Publications

Sohei Shimomai, Kei Ueda, Shinji Kimura
Input Data Format for Sparse Matrix in Quantum Annealing Emulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (3) (2024)
Zekun Wang, Shinichi Nishizawa, Shinji Kimura
An 8-point Approximate DCT Design with Optimized Signed Digit Encoding. SOCC (2023)
Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura
Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction. SOCC (2023)
Xianliang Ge, Shinji Kimura
Theory and Application of Topology-Based Exact Synthesis for Majority-Inverter Graphs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (9) (2023)
Sohei Shimomai, Kei Ueda, Shinji Kimura
Compressed Input Data Format of Quantum Annealing Emulator. DCC (2023)
Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura
Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks. SOCC (2023)
Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura
Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 70 (5) (2023)
Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura
A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery. SOCC (2023)
Takenori Aida, Akira Shionoya, Hirofumi Nonaka, Kouji Hayami, Hisashi Uchiyama, Masahiro Nagamori, Satoshi Ohhashi, Mai Kobayashi, Tsugumi Takayama, Shinji Kimura
Exploration of an Inflection Point of Ventilation Parameters with Anaerobic Threshold Using Strucchange. Sensors 22 (7) (2022)
Xianliang Ge, Shinji Kimura
Topology-Based Exact Synthesis for Majority Inverter Graph. ISCAS (2022)
Ke Ma, Shinji Kimura
ApproxTorch: An Approximate Multiplier Evaluation Environment for CNNs based on Pytorch. ISOCC (2022)
Rongyu Ding, Yi Guo, Heming Sun, Shinji Kimura
Energy-Efficient Approximate Floating-Point Multiplier Based on Radix-8 Booth Encoding. ASICON (2021)
Yi Guo, Heming Sun, Ping Lei, Shinji Kimura
Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2020)
Yi Guo, Heming Sun, Shinji Kimura
Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules. ASP-DAC (2020)
Jie Li, Yi Guo, Shinji Kimura
Accuracy-Configurable Low-Power Approximate Floating-Point Multiplier Based on Mantissa Bit Segmentation. TENCON (2020)
Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita
Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2019)
Yufeng Xu, Yi Guo, Shinji Kimura
Approximate Multiplier Using Reordered 4-2 Compressor with OR-based Error Compensation. ASICON (2019)
Yi Guo, Heming Sun, Ping Lei, Shinji Kimura
Design of Low-Cost Approximate Multipliers Based on Probability-Driven Inexact Compressors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Yi Guo, Heming Sun, Shinji Kimura
Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors. SoCC (2019)
Jinjia Zhou, Dajiang Zhou, Shuping Zhang, Shinji Kimura, Satoshi Goto
A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC. IEEE Trans. Circuits Syst. Video Technol. 28 (2) (2018)
Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura
Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression. ISCAS (2018)
Canran Jin, Heming Sun, Shinji Kimura
Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity. ASP-DAC (2018)
Zhenhao Liu, Yi Guo, Xiaoting Sun, Shinji Kimura
Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering. TENCON (2018)
Yi Guo, Heming Sun, Li Guo, Shinji Kimura
Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. APCCAS (2018)
Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura, Satoshi Goto
Lossy Compression for Embedded Computer Vision Systems. IEEE Access 6 (2018)
Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura
Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. ASP-DAC (2018)
Yi Guo, Heming Sun, Shinji Kimura
Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier. TENCON (2018)
Aya Ibrahim, Shuping Zhang, Federico Angiolini, Marcel Arditi, Shinji Kimura, Satoshi Goto, Jean-Philippe Thiran, Giovanni De Micheli
Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging. IEEE Trans. Biomed. Circuits Syst. 12 (5) (2018)
Xiaoting Sun, Yi Guo, Zhenhao Liu, Shinji Kimura
A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing. ICECS (2018)
Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura
Embedded Frame Compression for Energy-Efficient Computer Vision Systems. ISCAS (2018)
Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2017)
Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita
A low-cost approximate 32-point transform architecture. ISCAS (2017)
Heming Sun, Dajiang Zhou, Landan Hu, Shinji Kimura, Satoshi Goto
Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC. IEEE Trans. Multim. 19 (11) (2017)
Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura
Accelerating HEVC Inter Prediction with Improved Merge Mode Handling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2017)
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
Effective write-reduction method for MLC non-volatile memory. ISCAS (2017)
Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto
An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. IEEE J. Solid State Circuits 52 (1) (2017)
Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto
A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor. IEICE Trans. Electron. (3) (2017)
Fan Yang, Minghao Lin, Heming Sun, Shinji Kimura
Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. MWSCAS (2017)
Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura
CNN-MERP: An FPGA-Based Memory-Efficient Reconfigurable Processor for Forward and Backward Propagation of Convolutional Neural Networks. CoRR (2017)
Minghao Lin, Heming Sun, Shinji Kimura
Power-efficient and slew-aware three dimensional gated clock tree synthesis. VLSI-SoC (2016)
Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura
CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks. ICCD (2016)
Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. ICME Workshops (2016)
Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. CoRR (2016)
Xing Su, Shinji Kimura
Optimization of area and power in multi-mode power gating scheme for static memory elements. APCCAS (2016)
Heming Sun, Dajiang Zhou, Shuping Zhang, Shinji Kimura
A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. ISSCC (2016)
Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto
Low-Power Motion Estimation Processor with 3D Stacked Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Landan Hu, Heming Sun, Dajiang Zhou, Shinji Kimura
Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder. ICME Workshops (2015)
Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
An independent bandwidth reduction device for HEVC VLSI video system. ISCAS (2015)
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC (2015)
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura
Merge mode based fast inter prediction for HEVC. VCIP (2015)
Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto
Fast SAO estimation algorithm and its VLSI architecture. ICIP (2014)
Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto
Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto
An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder. VCIP (2014)
Naoya Okada, Yuichi Nakamura, Shinji Kimura
Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2013)
Zhe Du, Yu Jin, Shinji Kimura
Controlling-value-based power gating considering controllability propagation and power-off probability. ASICON (2013)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
An Exact Approach for GPC-Based Compressor Tree Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON (2013)
Shinji Kimura, Masaaki Fukuomoto, Tsutomu Horikoshi
Eyeglass-based hands-free videophone. ISWC (2013)
Yu Jin, Zhe Du, Shinji Kimura
Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Xin Man, Takashi Horiyama, Shinji Kimura
Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2012)
Yu Jin, Shinji Kimura
On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Yu Jin, Shinji Kimura
Multi-stage power gating based on controlling values of logic gates. ASICON (2011)
Ying Cui, Xiao Peng, Yu Jin, Peilin Liu, Shinji Kimura, Satoshi Goto
High-parallel LDPC decoder with power gating design. ASICON (2011)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Multi-Operand Adder Synthesis Targeting FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. ISLPED (2011)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Multi-operand adder synthesis on FPGAs using generalized parallel counters. ASP-DAC (2010)
Xin Man, Takashi Horiyama, Shinji Kimura
Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Chengjie Zang, Shinji Kimura
Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2009)
Lei Chen, Shinji Kimura
Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Masashi Tsuboi, Shinji Kimura, Tsutomu Horikoshi
An objective and subjective evaluation of an autostereoscopic 3d display. CHI Extended Abstracts (2009)
Shinji Kimura
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Yun Yang, Shinji Kimura
Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Synthesis of parallel prefix adders considering switching activities. ICCD (2008)
Chengjie Zang, Shigeki Imai, Steven Frank, Shinji Kimura
Issue Mechanism for Embedded Simultaneous Multithreading Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura
Fine-Grained Power Gating Based on the Controlling Value of Logic Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Yun Yang, Shinji Kimura
The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura
Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC (2006)
Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
Transition-based coverage estimation for symbolic model checking. ASP-DAC (2006)
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium (2005)
Shinji Kimura
Special Section on VLSI Design and CAD Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
Extended abstract: transition traversal coverage estimation for symbolic model checking. MEMOCODE (2005)
Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura
A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection. IPDPS (2005)
Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium (2004)
Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura
Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. ASP-DAC (2004)
Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, Katsumasa Watanabe
Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara
Folding of logic functions and its application to look up table compaction. ICCAD (2002)
Shinji Kimura, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe
Look Up Table Compaction Based on Folding of Logic Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
A real-time 64-monosyllable recognition LSI with learning mechanism. ASP-DAC (2001)
Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
Speech recognition chip for monosyllables. ASP-DAC (2001)
Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe
An application specific Java processor with reconfigurabilities. ASP-DAC (2000)
Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe
Multi-clock path analysis using propositional satisfiability. ASP-DAC (2000)
Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe
Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD (1998)
Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. CODES (1997)

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Publication Activity (10 Years)

Top Topics

Top Venues

Shinji Kimura