Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA.
Zhifeng ZhangDajiang ZhouShihao WangShinji KimuraPublished in: ASP-DAC (2018)
Keyphrases
- floating point
- convolutional neural networks
- convolutional network
- fixed point
- packing problem
- square root
- hardware implementation
- field programmable gate array
- low cost
- signal processing
- instruction set
- interval arithmetic
- floating point arithmetic
- embedded systems
- sparse matrices
- database management systems
- pairwise
- computer science