Atsushi Ishii

Publication Activity (10 Years)

Years Active: 2002-2016
Publications (10 Years): 1

Top Topics

Silicon Dioxide

High Efficiency

Top Venues

IEICE Trans. Commun.

Publications

Naoya Oikawa, Jiro Hirokawa, Hiroshi Nakano, Yasutake Hirachi, Hiroshi Isono, Atsushi Ishii, Makoto Ando
A 60GHz-Band High-Efficiency Antenna with a Thick Resin Layer and Differentially Fed through a Hole in a Silicon Chip. IEICE Trans. Commun. (1) (2016)
Jun Asano, Jiro Hirokawa, Hiroshi Nakano, Yasutake Hirachi, Hiroshi Isono, Atsushi Ishii, Makoto Ando
Manufacture and Performance of a 60GHz-Band High-Efficiency Antenna with a Thick Resin Layer and the Feed through a Hole in a Silicon Chip. IEICE Trans. Commun. (12) (2013)
Atsushi Ishii, Toyotaro Suzumura
Elastic Stream Computing with Clouds. IEEE CLOUD (2011)
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits 43 (1) (2008)
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC (2007)
Hiroshi Taguchi, Hiromitsu Shimakawa, Atsushi Ishii
Personalized Education Environment Considering Progress in C Programming Skill Acquisition. C5 (2004)
Shinji Kimura, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe
Look Up Table Compaction Based on Folding of Logic Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)