Masakazu Okada

Publication Activity (10 Years)

Years Active: 1998-2014
Publications (10 Years): 0

Top Topics

Data Collection

Integrated Circuit

Top Venues

IEICE Trans. Electron.

PerCom Workshops

Publications

Koichi Kuzume, Masakazu Okada
Sensor network system to promote energy conservation realization of energy smart school. PerCom Workshops (2014)
Masamitsu Tanaka, Atsushi Kitayama, Masakazu Okada, Tomohito Kouketsu, Takumi Takinami, Masato Ito, Akira Fujimaki
Nb Process Technology. IEICE Trans. Electron. (3) (2014)
Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors. IEICE Trans. Electron. (3) (2014)
Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. IEICE Trans. Electron. (8) (2008)
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits 43 (1) (2008)
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC (2007)
Kiyoto Watabe, Hajime Akiyama, Tomohide Terashima, Masakazu Okada, Shinji Nobuto, Masao Yamawaki, Sotoju Asa
An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI. IEEE J. Solid State Circuits 33 (9) (1998)