Kazuyoshi Takagi

Publication Activity (10 Years)

Years Active: 1998-2021
Publications (10 Years): 11

Top Topics

Runtime Environment

Integrated Circuit

Embedded Devices

Top Venues

IEICE Trans. Electron.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao
Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (11) (2021)
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices. J. Inf. Process. 28 (2020)
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ Trans. Syst. LSI Des. Methodol. 12 (2019)
Nobutaka Kito, Ryota Odaka, Kazuyoshi Takagi
Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing. IEICE Trans. Electron. (7) (2019)
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices. HEART (2019)
Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi
with Reduced Number of Matrix Multiplications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2018)
Pei-Yi Cheng, Kazuyoshi Takagi, Tsung-Yi Ho
Multi-terminal routing with length-matching for rapid single flux quantum circuits. ICCAD (2018)
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress. EMSOFT (2018)
Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi
RSFQ 4-bit Bit-Slice Integer Multiplier. IEICE Trans. Electron. (6) (2016)
Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation. IEICE Trans. Electron. (6) (2016)
Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi
An evaluation framework of OS-level power managements for the big.LITTLE architecture. NEWCAS (2016)
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi
A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. Inf. Media Technol. 10 (3) (2015)
Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits. IEICE Trans. Electron. (3) (2014)
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality. HPCC/CSS/ICESS (2014)
Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors. IEICE Trans. Electron. (3) (2014)
Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka
Nb Process. IEICE Trans. Electron. (3) (2014)
Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi
Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation. IEICE Trans. Electron. (3) (2014)
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis. ICA3PP (1) (2013)
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi
) suitable for implementation with a polynomial multiply instruction on GF(2). IET Comput. Digit. Tech. 6 (3) (2012)
Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition. IEICE Trans. Electron. (4) (2012)
Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi
Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits. IEICE Trans. Electron. (3) (2011)
Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki
Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm. IEICE Trans. Electron. (4) (2010)
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing. IEICE Trans. Inf. Syst. (2) (2010)
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. ISCAS (2008)
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2). IEEE Symposium on Computer Arithmetic (2007)
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2007)
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits. IEICE Trans. Electron. (12) (2007)
Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada
VLSI CAD Education and Exercise Course with Public Domain Tools. MSE (2007)
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi
A Hardware Algorithm for Integer Division Using the SD2 Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2006)
Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi
A transduction-based framework to synthesize RSFQ circuits. ASP-DAC (2006)
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi
A Hardware Algorithm for Integer Division. IEEE Symposium on Computer Arithmetic (2005)
Naofumi Takagi, Daisuke Matsuoka, Kazuyoshi Takagi
Digit-Recurrence Algorithm for Computing Reciprocal Square-Root. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2003)
Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi
) Based on Extended Binary GCD Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2002)
Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis. IEEE Trans. Computers 50 (5) (2001)
Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe
An application specific Java processor with reconfigurabilities. ASP-DAC (2000)
Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe
Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD (1998)