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A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing.

Kazuhiro NakamuraMasatoshi YamamotoKazuyoshi TakagiNaofumi Takagi
Published in: IEICE Trans. Inf. Syst. (2010)
Keyphrases
  • parallel processing
  • vlsi architecture
  • computational power
  • processing speed
  • parallel computation
  • real time
  • feature extraction
  • hidden markov models
  • neural network
  • distributed processing
  • vlsi implementation