Naofumi Takagi

Publication Activity (10 Years)

Years Active: 1982-2022
Publications (10 Years): 13

Top Topics

Integrated Circuit

Embedded Devices

Runtime Environment

Top Venues

IEICE Trans. Electron.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IPSJ Trans. Syst. LSI Des. Methodol.

IEICE Trans. Inf. Syst.

Publications

Takahiro Kawaguchi, Naofumi Takagi
32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor. IEICE Trans. Electron. (6) (2022)
Ryota Miyagi, Naofumi Takagi, Sho Kinoshista, Masashi Oda, Hideki Takase
Zytlebot : FPGA integrated ros-based autonomous mobile robot. FPT (2021)
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices. J. Inf. Process. 28 (2020)
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ Trans. Syst. LSI Des. Methodol. 12 (2019)
Nobutaka Kito, Naofumi Takagi
Concurrent Error Detectable Carry Select Adder with Easy Testability. IEEE Trans. Computers 68 (7) (2019)
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices. HEART (2019)
Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi
with Reduced Number of Matrix Multiplications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2018)
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress. EMSOFT (2018)
Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi
Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication. IEICE Trans. Inf. Syst. (3) (2017)
Naofumi Takagi
Recap of the 22nd Asia and South- Pacific Design Automation Conference. IEEE Des. Test 34 (3) (2017)
Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi
RSFQ 4-bit Bit-Slice Integer Multiplier. IEICE Trans. Electron. (6) (2016)
Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation. IEICE Trans. Electron. (6) (2016)
Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi
An evaluation framework of OS-level power managements for the big.LITTLE architecture. NEWCAS (2016)
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi
A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. Inf. Media Technol. 10 (3) (2015)
Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits. IEICE Trans. Electron. (3) (2014)
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality. HPCC/CSS/ICESS (2014)
Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors. IEICE Trans. Electron. (3) (2014)
Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka
Nb Process. IEICE Trans. Electron. (3) (2014)
Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa, Akira Fujimaki, Hiroyuki Akaike, Naofumi Takagi, Kazuaki J. Murakami
A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits. IEICE Trans. Electron. (3) (2014)
Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi
Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation. IEICE Trans. Electron. (3) (2014)
Nobutaka Kito, Naofumi Takagi
Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication. IEICE Trans. Inf. Syst. (9) (2013)
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis. ICA3PP (1) (2013)
Nobutaka Kito, Shinichi Fujii, Naofumi Takagi
A C-Testable Multiple-Block Carry Select Adder. IEICE Trans. Inf. Syst. (4) (2012)
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi
) suitable for implementation with a polynomial multiply instruction on GF(2). IET Comput. Digit. Tech. 6 (3) (2012)
Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition. IEICE Trans. Electron. (4) (2012)
Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi
Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits. IEICE Trans. Electron. (3) (2011)
Hirotaka Kawashima, Naofumi Takagi
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. Inf. Media Technol. 6 (4) (2011)
Hirotaka Kawashima, Naofumi Takagi
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Naofumi Takagi, Masamitsu Tanaka
Comparisons of Synchronous-Clocking SFQ Adders. IEICE Trans. Electron. (4) (2010)
Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki
Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm. IEICE Trans. Electron. (4) (2010)
Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka
Nb Multi-Layer Process. IEICE Trans. Electron. (4) (2010)
Nobutaka Kito, Kensuke Hanai, Naofumi Takagi
A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier. IEICE Trans. Inf. Syst. (10) (2010)
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing. IEICE Trans. Inf. Syst. (2) (2010)
Katsuki Kobayashi, Naofumi Takagi
Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions. IEEE Trans. Circuits Syst. II Express Briefs (8) (2009)
Nobutaka Kito, Naofumi Takagi
Level-Testability of Multi-operand Adders. ATS (2008)
Marcelo E. Kaihara, Naofumi Takagi
Bipartite Modular Multiplication Method. IEEE Trans. Computers 57 (2) (2008)
Katsuki Kobayashi, Naofumi Takagi
). IEEE Trans. Circuits Syst. II Express Briefs (11) (2008)
Naofumi Takagi, Kazuaki J. Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda
Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits. IEICE Trans. Electron. (3) (2008)
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. ISCAS (2008)
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2). IEEE Symposium on Computer Arithmetic (2007)
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2007)
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits. IEICE Trans. Electron. (12) (2007)
Fumio Kumazawa, Naofumi Takagi
Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2006)
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi
A Hardware Algorithm for Integer Division Using the SD2 Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2006)
Marcelo E. Kaihara, Naofumi Takagi
A Hardware Algorithm for Modular Multiplication/Division. IEEE Trans. Computers 54 (1) (2005)
Marcelo E. Kaihara, Naofumi Takagi
Bipartite Modular Multiplication. CHES (2005)
Marcelo E. Kaihara, Naofumi Takagi
A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi
A Hardware Algorithm for Integer Division. IEEE Symposium on Computer Arithmetic (2005)
Nhon T. Quach, Naofumi Takagi, Michael J. Flynn
Systematic IEEE rounding method for high-speed floating-point multipliers. IEEE Trans. Very Large Scale Integr. Syst. 12 (5) (2004)
Naofumi Takagi, Daisuke Matsuoka, Kazuyoshi Takagi
Digit-Recurrence Algorithm for Computing Reciprocal Square-Root. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2003)
Marcelo E. Kaihara, Naofumi Takagi
A VLSI Algorithm for Modular Multiplication/Division. IEEE Symposium on Computer Arithmetic (2003)
Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
Special Session: Security on SoC. ISSS (2002)
Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi
) Based on Extended Binary GCD Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2002)
Naofumi Takagi
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms. ISMVL (2002)
Naofumi Takagi
A Hardware Algorithm for Computing Reciprocal Square Root. IEEE Symposium on Computer Arithmetic (2001)
Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis. IEEE Trans. Computers 50 (5) (2001)
Akira Higuchi, Naofumi Takagi
) using projective coordinates. Inf. Process. Lett. 76 (3) (2000)
Naofumi Takagi, Seiji Kuwahara
A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector. IEEE Trans. Computers 49 (10) (2000)
Naofumi Takagi, Takashi Horiyama
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival. IEEE Trans. Computers 48 (1) (1999)
Naofumi Takagi, Seiji Kuwahara
Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector. IEEE Symposium on Computer Arithmetic (1999)
Naofumi Takagi
Powering by a Table Look-Up and a Multiplication with Operand Modification. IEEE Trans. Computers 47 (11) (1998)
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification. IEEE Trans. Computers 46 (4) (1997)
Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata
O(n)-Depth Modular Exponentiation Circuit Algorithm. IEEE Trans. Computers 46 (6) (1997)
Naofumi Takagi
Generating a Power of an Operand by a Table Look-up and a Multiplication. IEEE Symposium on Computer Arithmetic (1997)
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
Square Rooting by Iterative Multiply-Additions. Inf. Process. Lett. 60 (5) (1996)
Hannes Hassler, Naofumi Takagi
Function Evaluation by Table Look-up and Addition. IEEE Symposium on Computer Arithmetic (1995)
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root. IEEE Symposium on Computer Arithmetic (1995)
Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata
O(n)-depth circuit algorithm for modular exponentiation. IEEE Symposium on Computer Arithmetic (1995)
Naofumi Takagi
A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions. IEICE Trans. Inf. Syst. (10) (1995)
Naofumi Takagi
A modular multiplication algorithm with triangle additions. IEEE Symposium on Computer Arithmetic (1993)
Naofumi Takagi
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation. IEEE Trans. Computers 41 (8) (1992)
Naofumi Takagi, Shuzo Yajima
Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem. IEEE Trans. Computers 41 (7) (1992)
Naofumi Takagi, Shuzo Yajima
An on-line error-detectable high-speed array divider. Systems and Computers in Japan 22 (1) (1991)
Naofumi Takagi
A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications. IEEE Symposium on Computer Arithmetic (1991)
Naofumi Takagi, Tohru Asada, Shuzo Yajima
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation. IEEE Trans. Computers 40 (9) (1991)
Naofumi Takagi, Shuzo Yajima
An on-line error-detectable array divider with a redundant binary representation and a residue code. FTCS (1988)
Naofumi Takagi, Shuzo Yajima
On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic. IEEE Trans. Computers 36 (11) (1987)
Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima
On high-speed parallel algorithms using redundant coding. Systems and Computers in Japan 18 (12) (1987)
Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi
Design of high speed MOS multiplier and divider using redundant binary representation. IEEE Symposium on Computer Arithmetic (1987)
Naofumi Takagi, Tohru Asada, Shuzo Yajima
A hardware algorithm for computing sine and cosine using redundant binary representation. Systems and Computers in Japan 18 (8) (1987)
Naofumi Takagi, Shuzo Yajima
A square root hardware algorithm using redundant binary representation. Systems and Computers in Japan 17 (11) (1986)
Naofumi Takagi, Shuzo Yajima
Hardware algorithms for computing exponentials and logarithms using redundant binary representation. Systems and Computers in Japan 17 (12) (1986)
Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Trans. Computers 34 (9) (1985)
Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima
The Parallel Enumeration Sorting Scheme for VLSI. IEEE Trans. Computers 31 (12) (1982)