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Design of high speed MOS multiplier and divider using redundant binary representation.
Shigeo Kuninobu
Tamotsu Nishiyama
Hisakazu Edamatsu
Takashi Taniguchi
Naofumi Takagi
Published in:
IEEE Symposium on Computer Arithmetic (1987)
Keyphrases
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high speed
binary representation
design process
real time
low power
hardware implementation