Nobutaka Kito

Publication Activity (10 Years)

Years Active: 2008-2019
Publications (10 Years): 4

Top Topics

Mutual Exclusion

Error Detection

Top Venues

IEICE Trans. Inf. Syst.

IEICE Trans. Electron.

IPSJ Trans. Syst. LSI Des. Methodol.

IEEE Trans. Computers

Publications

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ Trans. Syst. LSI Des. Methodol. 12 (2019)
Nobutaka Kito, Ryota Odaka, Kazuyoshi Takagi
Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing. IEICE Trans. Electron. (7) (2019)
Nobutaka Kito, Naofumi Takagi
Concurrent Error Detectable Carry Select Adder with Easy Testability. IEEE Trans. Computers 68 (7) (2019)
Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi
Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication. IEICE Trans. Inf. Syst. (3) (2017)
Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits. IEICE Trans. Electron. (3) (2014)
Nobutaka Kito, Naofumi Takagi
Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication. IEICE Trans. Inf. Syst. (9) (2013)
Nobutaka Kito, Shinichi Fujii, Naofumi Takagi
A C-Testable Multiple-Block Carry Select Adder. IEICE Trans. Inf. Syst. (4) (2012)
Nobutaka Kito, Kensuke Hanai, Naofumi Takagi
A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier. IEICE Trans. Inf. Syst. (10) (2010)
Nobutaka Kito, Naofumi Takagi
Level-Testability of Multi-operand Adders. ATS (2008)