Kunihiro Asada

ORCID

Publication Activity (10 Years)

Years Active: 1992-2022
Publications (10 Years): 41

Top Venues

IEICE Trans. Electron.

ICECS

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEEE Trans. Instrum. Meas.

Publications

Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. (10) (2022)
Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Kunihiro Asada
Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. ICICDT (2021)
Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express 16 (19) (2019)
Daigo Takahashi, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. 68 (7) (2019)
Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2018)
Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34 (2) (2018)
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda
Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express 15 (5) (2018)
Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. (4) (2018)
Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) (2018)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. (4) (2018)
Nguyen Ngoc Mai Khanh, Shigeru Nakajima, Tetsuya Iizuka, Yoshio Mita, Kunihiro Asada
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. IEEE Trans. Instrum. Meas. 67 (4) (2018)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS (2018)
Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC (2018)
Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging (2017)
Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Extension of power supply impedance emulation method on ATE for multiple power domain. ETS (2017)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
CMOS-on-quartz pulse generator for low power applications. ASP-DAC (2017)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC (2017)
Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS (2017)
Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. (9) (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2017)
Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS (2017)
Nguyen Ngoc Mai Khanh, Kunihiro Asada
A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications. IEICE Trans. Electron. (12) (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS (2017)
Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS (2017)
Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. (10) (2016)
Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC (2016)
Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada
One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. EWME (2016)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. 25 (3) (2016)
Toru Nakura, Kunihiro Asada
Fully automated PLL compiler generating final GDS from specification. ISQED (2016)
James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada
A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. NEWCAS (2016)
Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC (2016)
Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE (2016)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Resonant power supply noise reduction using a triangular active charge injection. ICECS (2016)
Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. 32 (3) (2016)
Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC (2016)
Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. IEICE Trans. Electron. (2) (2016)
Masahiro Kano, Toru Nakura, Kunihiro Asada
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. ISQED (2016)
Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS (2016)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS (2015)
Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada
A Technique for Analyzing On-Chip Power Supply Impedance. ATS (2015)
Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. IEEE Trans. Instrum. Meas. 64 (4) (2015)
Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC (2015)
Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS (2015)
Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada
Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. IEICE Trans. Electron. (7) (2015)
Toru Nakura, Hiroaki Matsui, Kunihiro Asada
Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. IEICE Electron. Express 12 (3) (2015)
Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada
High-resolution measurement of magnetic field generated from cryptographic LSIs. SAS (2014)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
Burst-pulse Generator based on transmission line toward sub-MMW. DDECS (2014)
James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. ISCAS (2014)
Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada
A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2014)
Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. ATS (2014)
Hongbo Zhu, Kunihiro Asada
A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique. ICECS (2014)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2014)
Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC (2014)
Toru Nakura, Kunihiro Asada
Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. EWME (2014)
Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. DDECS (2014)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. IEICE Trans. Electron. (4) (2013)
Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. CICC (2013)
Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Pulse Width controlled PLL and its automated design flow. ICECS (2013)
Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. (4) (2013)
Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC (2013)
Tomohiko Yano, Toru Nakura, Kunihiro Asada
Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. ICECS (2013)
Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC (2013)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD (2013)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada
A novel test structure for measuring the threshold voltage variance in MOSFETs. ITC (2013)
James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. CICC (2013)
James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada
A design-for-test apparatus for measuring on-chip temperature with fine granularity. ISQED (2012)
Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Impact of All-Digital PLL on SoC Testing. Asian Test Symposium (2012)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. ASYNC (2012)
Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. (12) (2012)
Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira
A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium (2012)
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. (4) (2012)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. IEICE Trans. Electron. (4) (2012)
Tetsuya Iizuka, Kunihiro Asada
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Trans. Electron. (4) (2012)
Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC (2012)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. COOL Chips (2012)
Toru Nakura, Kunihiro Asada
Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Trans. Electron. (2) (2012)
Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada
Range extension of inductive coupling communication using multi-stage resonance. ISCIT (2012)
Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada
All-digital tunable power amplifier consuming 0.03mW/MHz using 0.18µm CMOS. IEICE Electron. Express 9 (12) (2012)
Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada
A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Trans. Electron. (4) (2012)
Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada
All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC (2012)
Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. (4) (2011)
Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC (2011)
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. (4) (2011)
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS (2011)
Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada
A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS. ASP-DAC (2011)
Teruki Nakasato, Toru Nakura, Kunihiro Asada
Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. ISOCC (2011)
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC (2011)
Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. (4) (2011)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC (2011)
Tetsuya Iizuka, Kunihiro Asada
All-digital ramp waveform generator for two-step single-slope ADC. IEICE Electron. Express 8 (1) (2011)
Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada
All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. ICECS (2011)
Shingo Mandai, Taihei Momma, Makoto Ikeda, Kunihiro Asada
Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method. IEICE Trans. Electron. (1) (2011)
Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. (6) (2011)
Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada
A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC (2011)
Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada
A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)

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Publication Activity (10 Years)

Top Topics

Top Venues

Kunihiro Asada