Takahiro J. Yamaguchi

Publication Activity (10 Years)

Years Active: 1997-2022
Publications (10 Years): 11

Top Topics

Image Rectification

High Signal To Noise Ratio

Special Session

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEICE Electron. Express

Publications

Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. ATS (2020)
Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
Theoretical Analysis of Noise Figure for Modulated Wideband Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters. IEEE Trans. Circuits Syst. (12) (2020)
Kiichi Niitsu, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. IEICE Electron. Express 16 (13) (2019)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS (2018)
James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada
A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. NEWCAS (2016)
Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS (2016)
Takahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki Kawabata, Masahiro Ishida, Koichiro Uekusa, Mani Soma
A new method for measuring alias-free aperture jitter in an ADC output. ITC (2015)
Tetsuya Iizuka, Takahiro J. Yamaguchi
Session 3 - Optical interconnect and reliability enhancement techniques. CICC (2015)
Kiichi Niitsu, Yusuke Osawa, Naohiro Harigai, Daiki Hirabayashi, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
A CMOS PWM Transceiver Using Self-Referenced Edge Detection. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Terri S. Fiez, Mike Peng Li
Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test. VTS (2014)
James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. ISCAS (2014)
Kiichi Niitsu, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
A low-offset cascaded time amplifier with reconfigurable inter-stage connection. IEICE Electron. Express 11 (10) (2014)
Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada
A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2014)
Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. ATS (2014)
Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas
Special session 12B: Panel post-silicon validation & test in huge variance era. VTS (2013)
Kiichi Niitsu, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines. IEICE Trans. Electron. (6) (2013)
Mike Peng Li, Takahiro J. Yamaguchi
Electrical and photonic I/O test and debug. CICC (2013)
Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada
A novel test structure for measuring the threshold voltage variance in MOSFETs. ITC (2013)
James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. CICC (2013)
Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuji Yano, Tatsuhiro Gake, Takahiro J. Yamaguchi, Nobukazu Takai
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. J. Electron. Test. 29 (6) (2013)
Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. ASP-DAC (2013)
Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation. IEEE J. Solid State Circuits 47 (11) (2012)
Takahiro J. Yamaguchi
Session Summary IV: Post-Silicon Measurements and Tests: Analog Test and High-Speed I/O Test II. Asian Test Symposium (2012)
Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira
A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium (2012)
Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. ASP-DAC (2012)
Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuta Arakawa, Daiki Hirabayashi, Yuji Yano, Tatsuhiro Gake, Nobukazu Takai, Takahiro J. Yamaguchi
Multi-bit sigma-delta TDC architecture with self-calibration. APCCAS (2012)
Kiichi Niitsu, Takahiro J. Yamaguchi, Masahiro Ishida, Haruo Kobayashi
Post-Silicon Jitter Measurements. Asian Test Symposium (2012)
Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. VLSIC (2012)
Masato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. ISOCC (2011)
Tomohiko Ogawa, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Satoshi Ito, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu
Design for Testability That Reduces Linearity Testing Time of SAR ADCs. IEICE Trans. Electron. (6) (2011)
Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada
An equivalent-time and clocked approach for continuous-time quantization. ISCAS (2011)
Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada
Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. ICECS (2011)
Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. A-SSCC (2011)
Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu
Application of a continuous-time level crossing quantization method for timing noise measurements. ITC (2011)
Tomohiko Ogawa, Haruo Kobayashi, Yohei Tan, Satoshi Ito, Satoshi Uemori, Nobukazu Takai, Kiichi Niitsu, Takahiro J. Yamaguchi, Tatsuji Matsuura, Nobuyoshi Ishikawa
SAR ADC that is configurable to optimize yield. APCCAS (2010)
Satoshi Uemori, Takahiro J. Yamaguchi, Satoshi Ito, Yohei Tan, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu, Nobuyoshi Ishikawa
ADC linearity test signal generation algorithm. APCCAS (2010)
Satoshi Ito, Shigeyuki Nishimura, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu
Stochastic TDC architecture with self-calibration. APCCAS (2010)
Albert Tumewu, Kazuyuki Miyazawa, Takafumi Aoki, Takahiro J. Yamaguchi, Katsuhiko Degawa, Takayuki Akita
Phase-based alignment of two signals having partially overlapped spectra. ICASSP (2009)
Takahiro J. Yamaguchi, Kiyotaka Ichiyama, X. H. Hou, Masahiro Ishida
A robust method for identifying a deterministic jitter model in a total jitter distribution. ITC (2009)
Takahiro J. Yamaguchi, Masahiro Ishida
Total Jitter Measurement for Testing HSIO Integrated SoCs. ATS (2008)
Takahiro J. Yamaguchi, Masayuki Kawabata, Mani Soma, Masahiro Ishida, K. Sawami, Koichiro Uekusa
A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing. ITC (2008)
Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma
Data jitter measurement using a delta-time-to-voltage converter method. ITC (2007)
Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma
Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter. CICC (2007)
Takahiro J. Yamaguchi
Top 5 Issues in Practical Testing of High-Speed Interface Devices. ATS (2007)
Takahiro J. Yamaguchi, H. X. Hou, Koji Takayama, Dave Armstrong, Masahiro Ishida, Mani Soma
An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test time. ITC (2007)
Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma
An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter. ISCAS (2007)
Takahiro J. Yamaguchi, Satoshi Iwamoto, Masahiro Ishida, Mani Soma
A Study of Per-Pin Timing Jitter Scope. ITC (2006)
Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma
A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement. ITC (2006)
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma
A wideband low-noise ATE-based method for measuring jitter in GHz signals. ITC (2005)
Kazuyuki Maruo, Masayoshi Ichikawa, Naoto Miyamoto, Leo Karnan, Takahiro J. Yamaguchi, Koji Kotani, Tadahiro Ohmi
A Dynamically-Reconfigurable Image Recognition Processor. IPDPS (2004)
Takahiro J. Yamaguchi
Loopback or not? ITC (2004)
Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai
A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. ITC (2004)
Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida
Skew measurements in clock distribution circuits using an analytic signal method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (7) (2004)
Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Toshifumi Watanabe, Tadahiro Ohmi
Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method. IEEE Trans. Circuits Syst. II Express Briefs 50 (6) (2003)
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha
Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division. J. Electron. Test. 19 (2) (2003)
Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha
Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements. ITC (2003)
Takahiro J. Yamaguchi
Open Architecture ATE and 250 Consecutive UIs. ITC (2003)
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha
Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. VTS (2002)
Takahiro J. Yamaguchi
Multi-GHz interface devices should be tested using external test resources. ITC (2002)
Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha
Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices. Asian Test Symposium (2002)
Takahiro J. Yamaguchi, Dong Sam Ha, Masahiro Ishida, Tadahiro Ohmi
A Method for Compressing Test Data Based on Burrows-Wheeler Transformation. IEEE Trans. Computers 51 (5) (2002)
Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie
A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. ITC (2002)
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. VTS (2001)
Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida
Testing clock distribution circuits using an analytic signal method. ITC (2001)
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Toshifumi Watanabe, Tadahiro Ohmi
Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method. VTS (2000)
Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe
microprocessor using an analytic signal method. ITC (2000)
Han Bin Kim, Dong Sam Ha, Takeshi Takahashi, Takahiro J. Yamaguchi
A new approach to built-in self-testable datapath synthesis based on integer linear programming. IEEE Trans. Very Large Scale Integr. Syst. 8 (5) (2000)
Masahiro Ishida, Dong Sam Ha, Takahiro J. Yamaguchi
COMPACT: A Hybrid Method for Compressing Test Data. VTS (1998)
Takahiro J. Yamaguchi
Static Testing of ADCs Using Wavelet Transforms. Asian Test Symposium (1997)
Takahiro J. Yamaguchi, Mani Soma
Dynamic Testing of ADCs Using Wavelet Transforms. ITC (1997)
Takahiro J. Yamaguchi, Masahiro Ishida, Marco Tilgner, Dong Sam Ha
An Efficient Method for Compressing Test Data. ITC (1997)