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Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Kiichi Niitsu
Osamu Kobayashi
Takahiro J. Yamaguchi
Haruo Kobayashi
Published in:
IEICE Electron. Express (2019)
Keyphrases
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theoretical analysis
high speed
power consumption
duty cycle
circuit design
power reduction
user interface
design decisions
design space
data sets
image processing
knowledge based systems
design process
computer aided
numerical simulations