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A Dynamically-Reconfigurable Image Recognition Processor.
Kazuyuki Maruo
Masayoshi Ichikawa
Naoto Miyamoto
Leo Karnan
Takahiro J. Yamaguchi
Koji Kotani
Tadahiro Ohmi
Published in:
IPDPS (2004)
Keyphrases
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image recognition
pattern recognition
image classification
parallel processing
high speed
single chip
face recognition
multi core processors
machine learning
instruction set
multi instance learning
parallel architectures
high end
computer architecture
feature vectors
neural network
wavelet packet decomposition