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An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation.

Kiichi NiitsuMasato SakuraiNaohiro HarigaiTakahiro J. YamaguchiHaruo Kobayashi
Published in: A-SSCC (2011)
Keyphrases
  • duty cycle
  • real time
  • high speed
  • clock frequency
  • high density
  • low cost
  • analog vlsi
  • packet loss
  • data structure
  • power consumption
  • dynamic range
  • cmos technology
  • evolvable hardware