Naohiro Harigai

Publication Activity (10 Years)

Years Active: 2011-2015
Publications (10 Years): 1

Top Topics

Design Methodology

Power Consumption

Top Venues

IEICE Electron. Express

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Kiichi Niitsu, Yusuke Osawa, Naohiro Harigai, Daiki Hirabayashi, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
A CMOS PWM Transceiver Using Self-Referenced Edge Detection. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Kiichi Niitsu, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
A low-offset cascaded time amplifier with reconfigurable inter-stage connection. IEICE Electron. Express 11 (10) (2014)
Kiichi Niitsu, Naohiro Harigai, Haruo Kobayashi
Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption. IEICE Electron. Express 10 (11) (2013)
Kiichi Niitsu, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines. IEICE Trans. Electron. (6) (2013)
Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. ASP-DAC (2013)
Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation. IEEE J. Solid State Circuits 47 (11) (2012)
Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. ASP-DAC (2012)
Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. VLSIC (2012)
Masato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. ISOCC (2011)
Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. A-SSCC (2011)