A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.
Kiichi NiitsuMasato SakuraiNaohiro HarigaiDaiki HirabayashiTakahiro J. YamaguchiHaruo KobayashiPublished in: ASP-DAC (2012)
Keyphrases
- cmos technology
- power consumption
- high speed
- nm technology
- low power
- analog vlsi
- silicon on insulator
- power dissipation
- metal oxide semiconductor
- wide dynamic range
- circuit design
- dynamic range
- low voltage
- power reduction
- mixed signal
- image sensor
- focal plane
- low cost
- power management
- packet loss
- parallel processing
- data center
- vlsi circuits
- real time
- clock frequency
- single chip
- integrated circuit
- duty cycle
- clock gating
- video camera
- face detection
- infrared