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A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Kiichi Niitsu
Naohiro Harigai
Daiki Hirabayashi
Daiki Oki
Masato Sakurai
Osamu Kobayashi
Takahiro J. Yamaguchi
Haruo Kobayashi
Published in:
VLSIC (2012)
Keyphrases
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duty cycle
high speed
power consumption
single phase
power reduction
database
image processing
wireless sensor networks
weighted graph
reduction method
phase information