Login / Signup
Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology.
Mohamed Abbas
Takahiro J. Yamaguchi
Yasuo Furukawa
Satoshi Komatsu
Kunihiro Asada
Published in:
ICECS (2011)
Keyphrases
</>
cmos technology
power dissipation
low power
power consumption
spl times
parallel processing
low voltage
clock frequency
image sensor
silicon on insulator
high speed
low cost
design methodology
finite state machines
digital signal processing
mixed signal
multimedia