Satoshi Komatsu

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 7

Top Topics

Projection Method

Practical Application

Edge Detection Algorithms

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

J. Electron. Test.

Publications

Kota Hara, Satoshi Komatsu
A PVT Variation Dependencies of VCO in Frequency Locked Loop. ICECS (2023)
Shinya Ubukata, Satoshi Komatsu
A Framework for Automatic Generation of Fully Synthesizable ADPLL. ICECS (2018)
Takumi Saito, Satoshi Komatsu
A low-voltage hysteresis comparator for low power applications. ICECS (2017)
Ryosuke Yumoto, Satoshi Komatsu
Characteristics optimization of stochastic ADC and its automatic generation system. NEWCAS (2017)
Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. (10) (2016)
James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada
A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. NEWCAS (2016)
Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. 32 (3) (2016)
James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. ISCAS (2014)
Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada
A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2014)
Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. ATS (2014)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2014)
Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC (2014)
Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC (2013)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD (2013)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada
A novel test structure for measuring the threshold voltage variance in MOSFETs. ITC (2013)
James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. CICC (2013)
Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira
A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium (2012)
Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC (2012)
Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada
An equivalent-time and clocked approach for continuous-time quantization. ISCAS (2011)
Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada
Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. ICECS (2011)
Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu
Application of a continuous-time level crossing quantization method for timing noise measurements. ITC (2011)
Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. DATE (2010)
Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2009)
Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD (2009)
Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada
Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. ETS (2009)
Satoshi Komatsu
VLSI Test Exercise Courses for Students in EE Department. ITC (2008)
Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Targeting Leakage Constraints during ATPG. ATS (2008)
Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita
Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC (2007)
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. ATVA (2007)
Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS (2007)
Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada
VLSI CAD Education and Exercise Course with Public Domain Tools. MSE (2007)
Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Dynamically reconfigurable protocol transducer. FPT (2006)
Satoshi Komatsu, Masahiro Fujita
An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. ISCAS (2006)
Yu Liu, Satoshi Komatsu, Masahiro Fujita
Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Yu Liu, Satoshi Komatsu, Masahiro Fujita
The AMS Extension to System Level Design Language - SpecC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
Synchronization Verification in System-Level Design with ILP Solvers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Satoshi Komatsu, Masahiro Fujita
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
Synchronization verification in system-level design with ILP solvers. MEMOCODE (2005)
Yu Liu, Satoshi Komatsu, Masahiro Fujita
AMS Extensions for Timed/Untimed System-Level Design Language. FDL (2005)
Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT (2005)
Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
System level design language extensions for timed/untimed digital-analog combined system design. ACM Great Lakes Symposium on VLSI (2005)
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima
Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS (2003)
Satoshi Komatsu, Masahiro Fujita
Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita
Engineering Changes in Field Modifiable Architectures. MEMOCODE (2003)
Satoshi Komatsu, Masahiro Fujita
Irredundant address bus encoding techniques based on adaptive codebooks for low power. ASP-DAC (2003)
Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada
Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE (2003)
Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita
Field modifiable architecture with FPGAs and its design methodology. FPT (2002)
Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS (2002)
Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. Great Lakes Symposium on VLSI (1999)
Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. ASP-DAC (1998)