Kenshu Seto

Publication Activity (10 Years)

Years Active: 2002-2021
Publications (10 Years): 5

Top Topics

Memory Footprint

Top Venues

IPSJ Trans. Syst. LSI Des. Methodol.

Inf. Media Technol.

Publications

Kenshu Seto
Scalar replacement in the presence of multiple write accesses for high-level synthesis. DATE (2021)
Kenshu Seto
Shift Register Initialization in Scalar Replacement for Reducing Code Size. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Kenshu Seto, Hamid Nejatollahi, Jiyoung An, Sujin Kang, Nikil D. Dutt
Small Memory Footprint Neural Network Accelerators. ISQED (2019)
Kenshu Seto
Scalar Replacement with Circular Buffers. IPSJ Trans. Syst. LSI Des. Methodol. 12 (2019)
Kenshu Seto
Scalar Replacement with Polyhedral Model. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018)
Shingo Kusakabe, Kenshu Seto
Forwarding Unit Generation for Loop Pipelining in High-level Synthesis. Inf. Media Technol. 9 (4) (2014)
Shingo Kusakabe, Kenshu Seto
Forwarding Unit Generation for Loop Pipelining in High-level Synthesis. IPSJ Trans. Syst. LSI Des. Methodol. 7 (2014)
Yuta Kato, Kenshu Seto
Loop Fusion with Outer Loop Shifting for High-level Synthesis. Inf. Media Technol. 8 (2) (2013)
Yuta Kato, Kenshu Seto
Loop Fusion with Outer Loop Shifting for High-level Synthesis. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Kenshu Seto, Masahiro Fujita
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2009)
Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki
SAT-based resource binding for reducing critical path delays. FPL (2008)
Kenshu Seto, Masahiro Fujita
Custom Instruction Generation with High-Level Synthesis. SASP (2008)
Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak
Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation. J. Satisf. Boolean Model. Comput. 5 (1-4) (2008)
Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita
Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC (2007)
Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS (2007)
Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Dynamically reconfigurable protocol transducer. FPT (2006)
Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT (2005)
Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima
Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS (2003)
Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita
Engineering Changes in Field Modifiable Architectures. MEMOCODE (2003)
Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita
Field modifiable architecture with FPGAs and its design methodology. FPT (2002)
Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS (2002)