Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.
Shanghua GaoKenshu SetoSatoshi KomatsuMasahiro FujitaPublished in: IESS (2007)
Keyphrases
- interconnection networks
- systolic array
- fault tolerant
- reconfigurable architecture
- parallel algorithm
- parallel architecture
- multistage
- high speed
- routing algorithm
- low cost
- message passing
- heterogeneous computing
- program synthesis
- general purpose
- focal plane
- functional programs
- programmable logic
- processing pipeline
- linear array
- neural architectures
- smart camera
- image processing
- parallel architectures
- multi agent