An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme.
Satoshi KomatsuMasahiro FujitaPublished in: ISCAS (2006)
Keyphrases
- low power
- high speed
- encoding scheme
- low cost
- cmos technology
- power consumption
- power dissipation
- single chip
- real time
- encoding schemes
- vlsi architecture
- vlsi circuits
- digital signal processing
- wireless transmission
- logic circuits
- high power
- low power consumption
- power reduction
- gate array
- highly efficient
- mixed signal
- digital camera
- pattern recognition
- genetic algorithm