Tetsuya Iizuka

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 70

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

ICICDT

ICECS

Publications

Sota Kano, Tetsuya Iizuka
150GHz Fundamental Oscillator Utilizing Transmission-Line-Based Inter-Stage Matching in 130nm SiGe BiCMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (5) (2024)
Haoming Zhang, Shuowei Li, Tetsuya Iizuka
A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit. IEEE Trans. Very Large Scale Integr. Syst. 32 (5) (2024)
Yuyang Zhu, Zunsong Yang, Masaru Osada, Haoming Zhang, Tetsuya Iizuka
Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (5) (2024)
Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham
A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. ISCAS (2024)
Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. IEEE J. Solid State Circuits 59 (7) (2024)
Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit. ICICDT (2023)
Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. VLSI Technology and Circuits (2023)
Hisashi Inoue, Hiroto Tamura, Ai Kitoh, Xiangyu Chen, Zolboo Byambadorj, Takeaki Yajima, Yasushi Hotta, Tetsuya Iizuka, Gouhei Tanaka, Isao H. Inoue
Long-time-constant leaky-integrating oxygen-vacancy drift-diffusion FET for human-interactive spiking reservoir computing. VLSI Technology and Circuits (2023)
Zhenyu Cheng, Zunsong Yang, Yuyang Zhu, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit. ICICDT (2023)
Haoming Zhang, Shuowei Li, Tetsuya Iizuka
Dynamic Circuit Characterization and a Single Ring-Oscillator-Based Test Structure for Its Timing Parameter Extraction. ICICDT (2023)
Haoyuan Gao, Hao Xu, Xinyi Lin, Yan Liu, Zhidong Tang, Xufeng Kou, Xingyu Zhang, Tetsuya Iizuka, Na Yan
INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications. ICTA (2023)
Ryoya Shibata, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka
Analysis of SAR ADC Performance Enhancement Utilizing Stochastic Resonance. IEEE Trans. Circuits Syst. II Express Briefs 70 (12) (2023)
Akira Matsuoka, Yo Kumano, Tomohiro Nezuka, Yoshikazu Furuta, Tetsuya Iizuka
A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation. IEEE Trans. Circuits Syst. II Express Briefs 70 (8) (2023)
Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. (10) (2022)
Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Masaru Osada, Zule Xu, Tetsuya Iizuka
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. ESSCIRC (2022)
Ryoya Shibata, Zule Xu, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka
A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. ISCAS (2022)
Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Xiangyu Chen, Takeaki Yajima, Hisashi Inoue, Isao H. Inoue, Zolboo Byambadorj, Tetsuya Iizuka
CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks. CoRR (2022)
Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. VLSI Technology and Circuits (2022)
Akira Matsuoka, Tomohiro Nezuka, Tetsuya Iizuka
Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Nguyen Ngoc Mai Khanh, Daisuke Yamazaki, Tetsuya Iizuka
140 GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS. ICICDT (2022)
Zule Xu, Naoki Ojima, Shuowei Li, Tetsuya Iizuka
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. IEEE Trans. Very Large Scale Integr. Syst. 29 (12) (2021)
Tetsuya Iizuka, Hao Xu, Asad A. Abidi
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW. ESSCIRC (2021)
Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Kunihiro Asada
Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. ICICDT (2021)
Zule Xu, Masaru Osada, Tetsuya Iizuka
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. VLSI Circuits (2021)
Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. ATS (2020)
Daisuke Yamazaki, Yoshitaka Otsuki, Takafumi Hara, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka
11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS. IET Circuits Devices Syst. 14 (3) (2020)
Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
Theoretical Analysis of Noise Figure for Modulated Wideband Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Masaru Osada, Zule Xu, Tetsuya Iizuka
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. VLSI Circuits (2020)
Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters. IEEE Trans. Circuits Syst. (12) (2020)
Yoshitaka Otsuki, Daisuke Yamazaki, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka
A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS. IEICE Electron. Express 16 (6) (2019)
Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express 16 (19) (2019)
Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express 16 (19) (2019)
Naoki Ojima, Zule Xu, Tetsuya Iizuka
6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS. NEWCAS (2019)
Daigo Takahashi, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. 68 (7) (2019)
Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2018)
Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34 (2) (2018)
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda
Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express 15 (5) (2018)
Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. (4) (2018)
Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) (2018)
Tetsuya Iizuka, Takaaki Ito, Asad A. Abidi
Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2018)
Tetsuya Iizuka, Asad A. Abidi
A Unified Analysis of the Signal Transfer Characteristics of a Single-Path FET-R-C Circuit. IEICE Trans. Electron. (7) (2018)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. (4) (2018)
Nguyen Ngoc Mai Khanh, Shigeru Nakajima, Tetsuya Iizuka, Yoshio Mita, Kunihiro Asada
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. IEEE Trans. Instrum. Meas. 67 (4) (2018)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS (2018)
Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC (2018)
Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging (2017)
Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Extension of power supply impedance emulation method on ATE for multiple power domain. ETS (2017)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
CMOS-on-quartz pulse generator for low power applications. ASP-DAC (2017)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC (2017)
Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS (2017)
Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. (9) (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2017)
Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS (2017)
Colin McAndrew, Tetsuya Iizuka
Session 4 - Modeling and measurement of mixed-signal circuits. CICC (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS (2017)
Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS (2017)
Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC (2016)
Tetsuya Iizuka, Asad A. Abidi
FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2016)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. 25 (3) (2016)
Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC (2016)
Tetsuya Iizuka, Asad A. Abidi
FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2016)
Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE (2016)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Resonant power supply noise reduction using a triangular active charge injection. ICECS (2016)
Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC (2016)
Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS (2016)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS (2015)
Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. IEEE Trans. Instrum. Meas. 64 (4) (2015)
Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC (2015)
Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS (2015)
Robert C. Aitken, Tetsuya Iizuka
Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospects. CICC (2015)
Tetsuya Iizuka, Takahiro J. Yamaguchi
Session 3 - Optical interconnect and reliability enhancement techniques. CICC (2015)
Stephane Le Tuai, Borivoje Nikolic, Tetsuya Iizuka, Ichiro Fujimori
F1: High-speed interleaved ADCs. ISSCC (2015)
Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada
High-resolution measurement of magnetic field generated from cryptographic LSIs. SAS (2014)
Manoj Sachdev, Tetsuya Iizuka
Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. CICC (2014)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2014)
Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. CICC (2013)
Boris Murmann, Tetsuya Iizuka
Session 26 overview: High-speed data converters. ISSCC (2013)
Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Pulse Width controlled PLL and its automated design flow. ICECS (2013)
Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC (2013)
Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC (2013)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD (2013)
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Impact of All-Digital PLL on SoC Testing. Asian Test Symposium (2012)
Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. (12) (2012)
Tetsuya Iizuka, Kunihiro Asada
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Trans. Electron. (4) (2012)
Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC (2012)
Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada
A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Trans. Electron. (4) (2012)
Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. (4) (2011)
Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC (2011)
Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. (4) (2011)
Tetsuya Iizuka, Kunihiro Asada
All-digital ramp waveform generator for two-step single-slope ADC. IEICE Electron. Express 8 (1) (2011)
Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. (6) (2011)
Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada
A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC (2011)
Tetsuya Iizuka, Kunihiro Asada
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS (2011)
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation. J. Next Gener. Inf. Technol. 2 (4) (2011)

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Publication Activity (10 Years)

Top Topics

Top Venues

Tetsuya Iizuka