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A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS.
Yoshitaka Otsuki
Daisuke Yamazaki
Nguyen Ngoc Mai Khanh
Tetsuya Iizuka
Published in:
IEICE Electron. Express (2019)
Keyphrases
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power consumption
high speed
clock gating
real time
data streams
computationally expensive
low power
neural network
cost effective
cmos technology