CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks.
Xiangyu ChenTakeaki YajimaHisashi InoueIsao H. InoueZolboo ByambadorjTetsuya IizukaPublished in: CoRR (2022)
Keyphrases
- analog vlsi
- spiking neural networks
- floating gate
- circuit design
- synaptic weights
- power consumption
- spiking neurons
- biologically inspired
- learning rules
- high speed
- neural network
- power dissipation
- focal plane
- chip design
- biologically plausible
- analog circuits
- flip flops
- mixed signal
- neural models
- low power
- feed forward
- neuron model
- learning strategies
- object recognition
- synaptic plasticity
- training data