Toru Nakura

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 39

Top Topics

Noise Reduction

Top Venues

IEICE Trans. Electron.

IEICE Electron. Express

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Yuto Yakubo, Kazuma Furutani, Kouhei Toyotaka, Haruki Katagiri, Masashi Fujita, Munehiro Kozuma, Yoshinori Ando, Yoshiyuki Kurokawa, Toru Nakura, Shunpei Yamazaki
Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating. ISSCC (2023)
Shinichi Nishizawa, Toru Nakura
Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. (10) (2022)
Shinichi Nishizawa, Toru Nakura
Density Aware Cell Library Design for Design-Technology Co-Optimization. ISQED (2022)
Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express 16 (19) (2019)
Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express 16 (19) (2019)
Daigo Takahashi, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. 68 (7) (2019)
Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2018)
Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34 (2) (2018)
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda
Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express 15 (5) (2018)
Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. (4) (2018)
Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) (2018)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. (4) (2018)
Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC (2018)
Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging (2017)
Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Extension of power supply impedance emulation method on ATE for multiple power domain. ETS (2017)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
CMOS-on-quartz pulse generator for low power applications. ASP-DAC (2017)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC (2017)
Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS (2017)
Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. (9) (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2017)
Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS (2017)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS (2017)
Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS (2017)
Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. (10) (2016)
Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC (2016)
Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada
One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. EWME (2016)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. 25 (3) (2016)
Toru Nakura, Kunihiro Asada
Fully automated PLL compiler generating final GDS from specification. ISQED (2016)
Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC (2016)
Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE (2016)
Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Resonant power supply noise reduction using a triangular active charge injection. ICECS (2016)
Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. 32 (3) (2016)
Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC (2016)
Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. IEICE Trans. Electron. (2) (2016)
Masahiro Kano, Toru Nakura, Kunihiro Asada
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. ISQED (2016)
Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS (2015)
Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada
A Technique for Analyzing On-Chip Power Supply Impedance. ATS (2015)
Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC (2015)
Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS (2015)
Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada
Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. IEICE Trans. Electron. (7) (2015)
Toru Nakura, Hiroaki Matsui, Kunihiro Asada
Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. IEICE Electron. Express 12 (3) (2015)
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
Burst-pulse Generator based on transmission line toward sub-MMW. DDECS (2014)
Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC (2014)
Toru Nakura, Kunihiro Asada
Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. EWME (2014)
Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. DDECS (2014)
Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
A Pulse Width controlled PLL and its automated design flow. ICECS (2013)
Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. (4) (2013)
Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC (2013)
Tomohiko Yano, Toru Nakura, Kunihiro Asada
Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. ICECS (2013)
Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
Impact of All-Digital PLL on SoC Testing. Asian Test Symposium (2012)
Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. (12) (2012)
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. (4) (2012)
Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC (2012)
Toru Nakura, Kunihiro Asada
Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Trans. Electron. (2) (2012)
Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC (2012)
Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. (4) (2011)
Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC (2011)
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. (4) (2011)
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS (2011)
Teruki Nakasato, Toru Nakura, Kunihiro Asada
Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. ISOCC (2011)
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC (2011)
Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. (4) (2011)
Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. (6) (2011)
Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2010)
Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC (2010)
Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
A 8bit two stage time-to-digital converter using time difference amplifier. IEICE Electron. Express 7 (13) (2010)
Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada
Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Trans. Electron. (3) (2010)
Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
Cascaded time difference amplifier using differential logic delay cell. ASP-DAC (2010)
Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC (2010)
Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS (2010)
MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ACM Great Lakes Symposium on VLSI (2009)
Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Trans. Electron. (6) (2009)
Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda
Measurement of power supply noise tolerance of self-timed processor. DDECS (2009)
Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. ESSCIRC (2009)
Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD (2009)
Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS (2009)
Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada
Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. ASP-DAC (2007)
Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada
LAGS System Using Data/Instruction Grain Power Control. ISSCC (2007)
Toru Nakura, Koichi Nose, Masayuki Mizuno
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. ISSCC (2007)
Toru Nakura, Makoto Ikeda, Kunihiro Asada
of Power Supply. IEICE Trans. Electron. (3) (2006)
Toru Nakura, Makoto Ikeda, Kunihiro Asada
Control of Power Supply for Margin Aware Operation. IEICE Trans. Electron. (11) (2006)
Toru Nakura, Makoto Ikeda, Kunihiro Asada
Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. IEICE Trans. Electron. (8) (2005)
Toru Nakura, Makoto Ikeda, Kunihiro Asada
Autonomous di/dt noise control scheme for margin aware operation. ESSCIRC (2005)
Toru Nakura, Makoto Ikeda, Kunihiro Asada
Detector Circuit. IEICE Trans. Electron. (5) (2005)
Toru Nakura, Makoto Ikeda, Kunihiro Asada
Stub vs. Capacitor for Power Supply Noise Reduction. IEICE Trans. Electron. (1) (2005)
Toru Nakura, Makoto Ikeda, Kunihiro Asada
Theoretical study of stubs for power line noise reduction [LSI applications]. CICC (2003)
Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits 35 (5) (2000)