A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment.
Benjamin Stefan DevlinToru NakuraMakoto IkedaKunihiro AsadaPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2010)
Keyphrases
- low power
- high throughput
- high speed
- low cost
- cmos technology
- single chip
- low latency
- data acquisition
- power reduction
- power consumption
- low power consumption
- gate array
- genome wide
- proteomic data
- nm technology
- microarray
- systems biology
- digital signal processing
- biological data
- energy dissipation
- vlsi circuits
- power dissipation
- power saving
- logic circuits
- mixed signal
- image sensor
- mass spectrometry data
- real time
- ultra low power
- delay insensitive
- low voltage
- mass spectrometry
- protein protein interactions
- microarray data
- silicon on insulator
- digital camera
- data processing
- database systems