Benjamin Stefan Devlin

Publication Activity (10 Years)

Years Active: 2009-2013
Publications (10 Years): 0

Top Topics

Labor Intensive

Electrical Energy

Top Venues

IEICE Trans. Electron.

Publications

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. IEICE Trans. Electron. (4) (2013)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. ASYNC (2012)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. IEICE Trans. Electron. (4) (2012)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. COOL Chips (2012)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC (2011)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. ICECS (2011)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. IEEE J. Solid State Circuits 46 (11) (2011)
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. ISLPED (2011)
Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2010)
Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe
Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. DFT (2010)
Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. ESSCIRC (2009)