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A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation.
Benjamin Stefan Devlin
Makoto Ikeda
Kunihiro Asada
Published in:
IEEE J. Solid State Circuits (2011)
Keyphrases
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computationally efficient
levels of abstraction
hardware implementation
parallel architecture
computer systems
data flow
real time image processing
asynchronous communication
nm technology