Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA.
Benjamin Stefan DevlinMakoto IkedaKunihiro AsadaPublished in: ISLPED (2011)
Keyphrases
- power reduction
- hardware implementation
- power consumption
- low cost
- field programmable gate array
- systolic array
- energy management
- parallel architecture
- digital signal
- high speed
- energy efficiency
- reconfigurable architecture
- power saving
- minimum energy
- hardware design
- general purpose
- energy saving
- data flow
- higher level
- low power
- energy minimization
- power generation
- real time image processing
- energy consumption