647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA.
Benjamin Stefan DevlinMyeongGyu JeongToru NakuraMakoto IkedaKunihiro AsadaPublished in: ESSCIRC (2009)
Keyphrases
- high speed
- fpga device
- xilinx virtex
- hardware implementation
- cmos technology
- nm technology
- field programmable gate array
- real time
- low power
- signal processing
- real time image processing
- power consumption
- hardware architecture
- block wise
- power reduction
- fpga hardware
- verilog hdl
- block size
- low cost
- asynchronous communication
- digital signal
- fpga implementation
- single chip
- fpga technology
- multiresolution