Zule Xu

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 24

Top Topics

Behavioral Model

Top Venues

IEICE Trans. Electron.

IEEE J. Solid State Circuits

Publications

Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. IEEE J. Solid State Circuits 59 (7) (2024)
Anoop Narayan Bhat, Paul Mateman, Zule Xu, Peter Vis, Paul Detterer, Gururaja Kasanadi Ramachandra, Yunus Baykal, Mario Konijnenburg, Yao-Hong Liu, Christian Bachmann, Peng Zhang
23.5 A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End. ISSCC (2024)
Masaya Miyahara, Zule Xu, Takehito Ishii, Noritoshi Kimura
A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications. IEICE Trans. Electron. 106 (10) (2023)
Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Masaru Osada, Zule Xu, Tetsuya Iizuka
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. ESSCIRC (2022)
Ryoya Shibata, Zule Xu, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka
A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. ISCAS (2022)
Zule Xu
A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration. IEEE J. Solid State Circuits 57 (10) (2022)
Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. VLSI Technology and Circuits (2022)
Zule Xu, Naoki Ojima, Shuowei Li, Tetsuya Iizuka
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. IEEE Trans. Very Large Scale Integr. Syst. 29 (12) (2021)
Zule Xu
A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving -232.8-dB FoMref. A-SSCC (2021)
Zule Xu, Masaru Osada, Tetsuya Iizuka
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. VLSI Circuits (2021)
Masaru Osada, Zule Xu, Tetsuya Iizuka
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. VLSI Circuits (2020)
Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC (2019)
Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. (7) (2019)
Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express 16 (19) (2019)
Naoki Ojima, Zule Xu, Tetsuya Iizuka
6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS. NEWCAS (2019)
Yasushi Fukuda, Zule Xu, Takayuki Kawahara
Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error. IEICE Trans. Electron. (12) (2017)
Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. IEICE Trans. Electron. (6) (2017)
Zule Xu, Takayuki Kawahara
A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design. IEICE Trans. Electron. (4) (2017)
Mitsutoshi Sugawara, Zule Xu, Akira Matsuzawa
Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs. IEICE Trans. Electron. (6) (2017)
Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. IEEE J. Solid State Circuits 51 (10) (2016)
Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. ISCAS (2016)
Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC (2016)
Zule Xu, Masaya Miyahara, Akira Matsuzawa
A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. A-SSCC (2015)
Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2015)
James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. A-SSCC (2014)
Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. CICC (2013)
Zule Xu, Masaya Miyahara, Akira Matsuzawa
A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS. NEWCAS (2013)
Jun Gyu Lee, Zule Xu, Shoichi Masui
Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2012)
Zule Xu, Jun Gyu Lee, Shoichi Masui
Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL. IEICE Trans. Electron. (6) (2011)