Masaya Miyahara

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 36

Top Topics

Cmos Technology

Replica Selection

Top Venues

IEICE Trans. Electron.

IEEE J. Solid State Circuits

Publications

Masaya Miyahara, Zule Xu, Takehito Ishii, Noritoshi Kimura
A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications. IEICE Trans. Electron. 106 (10) (2023)
Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Jian Pang, Hanli Liu, Masaya Miyahara, Atsushi Shirane, Kenichi Okada
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. IEEE J. Solid State Circuits 56 (12) (2021)
Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. IEEE J. Solid State Circuits 54 (5) (2019)
Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. (7) (2019)
Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC (2019)
Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa
A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells. IEICE Trans. Electron. (4) (2018)
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS. IEEE J. Solid State Circuits 53 (10) (2018)
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
A 7GS/s Complete-DDFS-Solution in 65nm CMOS. IEICE Trans. Electron. (4) (2018)
Akira Matsuzawa, Masaya Miyahara
SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier. IEICE Electron. Express 15 (5) (2018)
Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. VLSI Circuits (2018)
Akira Matsuzawa, Masaya Miyahara
SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. ASICON (2017)
Masaya Miyahara, Akira Matsuzawa
An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. CICC (2017)
Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits 52 (11) (2017)
Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC (2017)
Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. IEICE Trans. Electron. (6) (2017)
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS. A-SSCC (2017)
Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON (2017)
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS. ESSCIRC (2017)
Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa
A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input. IEICE Trans. Electron. (6) (2017)
Yu Hou, Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
-Order Noise Shaping in 65nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Lilan Yu, Masaya Miyahara, Akira Matsuzawa
A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers. A-SSCC (2016)
Lilan Yu, Masaya Miyahara, Akira Matsuzawa
Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques. IEICE Trans. Electron. (6) (2016)
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits 51 (6) (2016)
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture. IEICE Trans. Electron. (10) (2016)
Lilan Yu, Masaya Miyahara, Akira Matsuzawa
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers. IEEE J. Solid State Circuits 51 (10) (2016)
Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
order fully-passive noise-shaping SAR ADC with embedded passive gain. A-SSCC (2016)
Tohru Kaneko, Yuya Kimura, Koji Hirose, Masaya Miyahara, Akira Matsuzawa
A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter. ESSCIRC (2016)
Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. IEEE J. Solid State Circuits 51 (10) (2016)
Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. ISCAS (2016)
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder. ESSCIRC (2016)
Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC (2016)
Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. A-SSCC (2016)
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC. IEICE Trans. Electron. (6) (2016)
Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC (2016)
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC. IEICE Trans. Electron. (8) (2016)
James Lin, Ibuki Mano, Masaya Miyahara, Akira Matsuzawa
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Zule Xu, Masaya Miyahara, Akira Matsuzawa
A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. A-SSCC (2015)
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture. ASICON (2015)
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC (2015)
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC. VLSIC (2015)
Tohru Kaneko, Masaya Miyahara, Akira Matsuzawa
A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency. IEICE Trans. Electron. (4) (2015)
Lilan Yu, Masaya Miyahara, Akira Matsuzawa
A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers. A-SSCC (2015)
James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers. IEEE J. Solid State Circuits 50 (6) (2015)
Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
19.5 An HCI-healing 60GHz CMOS transceiver. ISSCC (2015)
Yu Hou, Takamoto Watanabe, Masaya Miyahara, Akira Matsuzawa
An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2015)
Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2015)
Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa
22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. ISSCC (2014)
Takamoto Watanabe, Yu Hou, Masaya Miyahara, Akira Matsuzawa
reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS. ICECS (2014)
James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. A-SSCC (2014)
Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits 49 (1) (2014)
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC (2014)
Jeonghoon Han, Masaya Miyahara, Akira Matsuzawa
Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator. IEICE Trans. Electron. (4) (2014)
Tomohito Terasawa, Yuji Kamiya, Hiroyuki Kawashima, Kenichiro Imai, Masanobu Suzuki, Takamoto Watanabe, Nobuyuki Taguchi, Manabu Sawada, Yu Hou, Yoshiyuki Hirooka, Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa
Radio receiver front-end using time-based all-digital ADC (TAD). ICECS (2014)
James Lin, Masaya Miyahara, Akira Matsuzawa
An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. ISSCC (2014)
Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa
A 7-bit 1-GS/s Flash ADC with Background Calibration. IEICE Trans. Electron. (4) (2014)
James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers. CICC (2013)
Fei Li, Masaya Miyahara, Akira Matsuzawa
Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs. IEICE Trans. Electron. (4) (2013)
Fei Li, Masaya Miyahara, Akira Matsuzawa
A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs. IEICE Trans. Electron. (6) (2013)
Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells. IEICE Trans. Electron. (6) (2013)
Hyunui Lee, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa
A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2013)
Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. IEEE J. Solid State Circuits 48 (1) (2013)
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. ISSCC (2013)
Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. CICC (2013)
Zule Xu, Masaya Miyahara, Akira Matsuzawa
A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS. NEWCAS (2013)
Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
A 12-bit interpolated pipeline ADC using body voltage controlled amplifier. NEWCAS (2013)
Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers. IEICE Trans. Electron. (6) (2013)
Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa
A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching. IEICE Trans. Electron. (6) (2012)
Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. ISSCC (2012)
Daehwa Paik, Masaya Miyahara, Akira Matsuzawa
An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2012)
James Lin, Masaya Miyahara, Akira Matsuzawa
A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique. ISCAS (2011)
Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa
A time-domain architecture and design method of high speed A-to-D converters with standard cells. A-SSCC (2011)
Daehwa Paik, Masaya Miyahara, Akira Matsuzawa
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration. ASICON (2011)
Daehwa Paik, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa
An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Kaziiya Kojima, Yasuhiro Toriyama, Toru Taniguchi, Masaya Miyahara, Akira Matsuzawa
Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof. ICECS (2009)
Masaya Miyahara, Akira Matsuzawa
A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Masaya Miyahara, Akira Matsuzawa
The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time. IEICE Trans. Electron. (6) (2007)