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A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation.
Wei Deng
Ahmed Musa
Teerachot Siriburanon
Masaya Miyahara
Kenichi Okada
Akira Matsuzawa
Published in:
ASP-DAC (2014)
Keyphrases
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high speed
circuit design
mixed signal
camera calibration
low cost
power consumption
gaze estimation
cmos image sensor
phase locked loop
camera parameters
high density
single chip
physical design
low power
primal dual
digital libraries
analog vlsi
metal oxide semiconductor