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25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture.

Teerachot SiriburanonSatoshi KondoKento KimuraTomohiro UenoSatoshi KawashimaTohru KanekoWei DengMasaya MiyaharaKenichi OkadaAkira Matsuzawa
Published in: ISSCC (2015)
Keyphrases
  • sigma delta
  • power consumption
  • analog to digital converter
  • random sampling
  • management system
  • high speed
  • real time
  • low cost
  • software architecture
  • network architecture
  • power supply
  • mixed signal