A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.
Teerachot SiriburanonSatoshi KondoKento KimuraTomohiro UenoSatoshi KawashimaTohru KanekoWei DengMasaya MiyaharaKenichi OkadaAkira MatsuzawaPublished in: IEEE J. Solid State Circuits (2016)