Sanroku Tsukamoto

Publication Activity (10 Years)

Years Active: 1996-2017
Publications (10 Years): 2

Top Topics

Calibration Method

Analog To Digital Converter

Top Venues

IEEE J. Solid State Circuits

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Satoshi Matsubara, Hirotaka Tamura, Motomu Takatsu, Danny Yoo, Behraz Vatankhahghadim, Hironobu Yamasaki, Toshiyuki Miyazawa, Sanroku Tsukamoto, Yasuhiro Watanabe, Kazuya Takemoto, Ali Sheikholeslami
Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine. CISIS (2017)
Sanroku Tsukamoto
Advances in Analog-to-Digital Converters over the Last Decade. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2017)
Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. IEEE J. Solid State Circuits 50 (4) (2015)
Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS. IEEE J. Solid State Circuits 49 (3) (2014)
Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro
7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. VLSIC (2014)
Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa
A 7-bit 1-GS/s Flash ADC with Background Calibration. IEICE Trans. Electron. (4) (2014)
Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. IEEE J. Solid State Circuits 48 (12) (2013)
Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. ISSCC (2013)
Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS. VLSI-DAT (2012)
Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. VLSI-DAT (2012)
Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration. IEICE Trans. Electron. (6) (2012)
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. (3) (2010)
Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration. ISSCC (2010)
Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto
A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration. IEEE Trans. Biomed. Circuits Syst. 4 (6) (2010)
Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda
A 1 GHz CMOS comparator with dynamic offset control technique. ASP-DAC (2009)
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
Split capacitor DAC mismatch calibration in successive approximation ADC. CICC (2009)
Masashi Kijima, Kenji Ito, Kuniyoshi Kamei, Sanroku Tsukamoto
A 6b 3GS/s flash ADC with background calibration. CICC (2009)
Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
A dynamic offset control technique for comparator design in scaled CMOS technology. CICC (2008)
Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 43 (12) (2008)
Masato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto
A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing. ISSCC (2007)
Sanroku Tsukamoto, William G. Schofield, Toshiaki Endo
A CMOS 6-b, 400-MSample/s ADC with error correction. IEEE J. Solid State Circuits 33 (12) (1998)
Sanroku Tsukamoto, I. Dedic, Toshiaki Endo, K. y. Kikuta, K. Goto, O. Kobayashi
A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI. IEEE J. Solid State Circuits 31 (11) (1996)