Yasumoto Tomita

Publication Activity (10 Years)

Years Active: 2005-2020
Publications (10 Years): 10

Top Topics

Diagrammatic Reasoning

Gpu Accelerated

Top Venues

Publications

Amir Haderbache, Koichi Shirahata, Takuji Yamamoto, Yasumoto Tomita, Hiroshi Okuda
Acceleration of Structural Analysis Simulations using CNN-based Auto-Tuning of Solver Tolerance. IPDPS Workshops (2020)
Takuya Fukagai, Kyosuke Maeda, Satoshi Tanabe, Koichi Shirahata, Yasumoto Tomita, Atsushi Ike, Akira Nakagawa
Speed-Up of Object Detection Neural Network with GPU. ICIP (2018)
Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita
An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. IEEE J. Solid State Circuits 53 (4) (2018)
Koichi Shirahata, Youri Coppens, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike
GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning. Int. J. Netw. Comput. 8 (2) (2018)
Song Wang, Li Sun, Wei Fan, Jun Sun, Satoshi Naoi, Koichi Shirahata, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike, Tetsutaro Hashimoto
An automated CNN recommendation system for image classification tasks. ICME (2017)
Youri Coppens, Koichi Shirahata, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike
GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning. CANDAR (2017)
Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, Yasumoto Tomita, Takayuki Baba, Yasuhiro Watanabe
An FPGA-accelerated partial duplicate image retrieval engine for a document search system. WACV (2016)
Koichi Shirahata, Yasumoto Tomita, Atsushi Ike
Memory reduction method for deep neural network training. MLSP (2016)
Song Wang, Li Sun, Wei Fan, Jun Sun, Satoshi Naoi, Koichi Shirahata, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike
An Automated CNN Recommendation System for Image Classification Tasks. CoRR (2016)
Takashi Shimizu, Yasumoto Tomita, Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, David Thach, Takashi Miyoshi, Takayuki Baba, Yasuhiro Watanabe, Atsushi Ike
An FPGA-accelerated partial image matching engine for massive media data searching systems. VLSI Circuits (2016)
Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. VLSIC (2014)
Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara
What is a good way to expand a silicon value to a solution value? A-SSCC (2014)
Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto
A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. ISSCC (2010)
Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits 45 (10) (2010)
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. (3) (2010)
Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers. CICC (2010)
Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC (2010)
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
Split capacitor DAC mismatch calibration in successive approximation ADC. CICC (2009)
Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
A dynamic offset control technique for comparator design in scaled CMOS technology. CICC (2008)
Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. IEEE J. Solid State Circuits 42 (3) (2007)
Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. ISSCC (2006)
Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS. IEEE J. Solid State Circuits 40 (4) (2005)