Hisakatsu Yamaguchi

Publication Activity (10 Years)

Years Active: 2003-2021
Publications (10 Years): 10

Top Topics

Top Venues

IEEE J. Solid State Circuits

Publications

Hisakatsu Yamaguchi, Makiko Ito, Katsuhiro Yoda, Atsushi Ike
Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management. DATE (2021)
Jun Matsui, Hisakatsu Yamaguchi
Event-Driven Model for High Speed End-to-End Simulations of Transmission System with Non-Linear Optical Elements and Cascaded Clock-and-Data Recovery Circuits. VLSI-DAT (2019)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs. IEEE J. Solid State Circuits 53 (9) (2018)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR. IEEE J. Solid State Circuits 53 (3) (2018)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
Jitter injection for on-chip jitter measurement in PI-based CDRs. CICC (2017)
Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS. IEEE J. Solid State Circuits 52 (12) (2017)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. ISSCC (2017)
Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. ISSCC (2017)
Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. ISSCC (2016)
Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits (2016)
Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon
F6: Energy-efficient I/O design for next-generation systems. ISSCC (2014)
Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. VLSIC (2014)
Ken Chang, Hisakatsu Yamaguchi
Session 2 overview: Ultra-high-speed transceivers and equalizers. ISSCC (2013)
Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi
F3: Emerging technologies for wireline communication. ISSCC (2013)
Ken Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John T. Stonick, Hisakatsu Yamaguchi
10-40 Gb/s I/O design for data communications. ISSCC (2012)
Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto
A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. ISSCC (2010)
Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. IEEE J. Solid State Circuits 45 (6) (2010)
Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC (2010)
Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. IEEE J. Solid State Circuits 43 (3) (2008)
Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2008)
Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
18-GHz Clock Distribution Using a Coupled VCO Array. IEICE Trans. Electron. (4) (2007)
Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. IEICE Trans. Electron. (3) (2006)
Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura
A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process. CICC (2005)
Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura
A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization. IEEE J. Solid State Circuits 40 (4) (2005)
Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura
A CMOS multichannel 10-Gb/s transceiver. IEEE J. Solid State Circuits 38 (12) (2003)