Ali Sheikholeslami

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 36

Top Topics

Steerable Pyramid

Quadratic Optimization

Top Venues

IEEE Open J. Circuits Syst.

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
A Low-Power High-BW PAM4 VCSEL Driver With Three-Tap FFE in 12-nm CMOS FinFET Process. IEEE J. Solid State Circuits 59 (7) (2024)
Pierre Miasnikof, Mohammad Bagherbeik, Ali Sheikholeslami
Graph clustering with Boltzmann machines. Discret. Appl. Math. 343 (2024)
Jeremy Cosson-Martin, Jhoan Salinas, Hossein Shakiba, Ali Sheikholeslami
FBMC vs. PAM and DMT for High-Speed Wireline Communication. IEEE Open J. Circuits Syst. 5 (2024)
Mohammad Emami Meybodi, Hossein Shakiba, Ali Sheikholeslami
Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication. IEEE Open J. Circuits Syst. 5 (2024)
Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET. VLSI Technology and Circuits (2023)
Jeremy Cosson-Martin, Miad Laghaei, Hossein Shakiba, Ali Sheikholeslami
Efficient PAPR Reduction for Discrete Multi-Tone Signalling in High-Speed Wireline Applications. MWSCAS (2023)
Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
A 0.82pJ/b 50Gb/s PAM4 VCSEL Driver with 3-Tap Asymmetric FFE in 12nm CMOS FinFET Process. ESSCIRC (2023)
Sigeng Chen, Jeffrey S. Rosenthal, Aki Dote, Hirotaka Tamura, Ali Sheikholeslami
Optimization via Rejection-Free Partial Neighbor Search. Stat. Comput. 33 (6) (2023)
Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process. IEEE Open J. Circuits Syst. 4 (2023)
Mohammad Emami Meybodi, Hector Gomez, Yu-Chun Lu, Hossein Shakiba, Ali Sheikholeslami
Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE). IEEE Open J. Circuits Syst. 3 (2022)
Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization. VLSI Technology and Circuits (2022)
Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA. FPGA (2022)
Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier. IEEE Open J. Circuits Syst. 3 (2022)
Pierre Miasnikof, Mohammad Bagherbeik, Ali Sheikholeslami
Graph clustering with Boltzmann machines. CoRR (2022)
Jeremy Cosson-Martin, Hossein Shakiba, Ali Sheikholeslami
An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications. IEEE Open J. Circuits Syst. 3 (2022)
Mohammad Bagherbeik, Ali Sheikholeslami
Caching and Vectorization Schemes to Accelerate Local Search Algorithms for Assignment Problems. CEC (2021)
Ali Sheikholeslami
The Power of Parallelism in Stochastic Search for Global Optimum: Keynote Paper. ESSCIRC (2021)
Jeremy Cosson-Martin, Hossein Shakiba, Ali Sheikholeslami
Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications. IEEE Open J. Circuits Syst. 2 (2021)
Jhoan Salinas, Jeremy Cosson-Martin, Miad Laghaei, Hossein Shakiba, Ali Sheikholeslami
Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication. IEEE Open J. Circuits Syst. 2 (2021)
Jeffrey S. Rosenthal, Aki Dote, Keivan Dabiri, Hirotaka Tamura, Sigeng Chen, Ali Sheikholeslami
Jump Markov chains and rejection-free Metropolis algorithms. Comput. Stat. 36 (4) (2021)
Mehrdad Malekmohammadi, Keivan Dabiri, Joshua Mathews, Daryl Nazareth, Hirotaka Tamura, Ali Sheikholeslami
A Hamiltonian Engine for Radiotherapy Optimization. EMBC (2020)
Mohammad Bagherbeik, Parastoo Ashtari, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems. PPSN (1) (2020)
Keivan Dabiri, Mehrdad Malekmohammadi, Ali Sheikholeslami, Hirotaka Tamura
Replica Exchange MCMC Hardware With Automatic Temperature Selection and Parallel Trial. IEEE Trans. Parallel Distributed Syst. 31 (7) (2020)
Ali Sheikholeslami
Keynote II: Digital Annealer: A Stochastic Search for Global Optimum. ISMVL (2020)
Mohammad Javad-Kalbasi, Keivan Dabiri, Shahrokh Valaee, Ali Sheikholeslami
Digitally Annealed Solution for the Vertex Cover Problem with Application in Cyber Security. ICASSP (2019)
Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki
A 30Gb/s 2x Half-Baud-Rate CDR. CICC (2019)
Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki
A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS. ISSCC (2019)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs. IEEE J. Solid State Circuits 53 (9) (2018)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR. IEEE J. Solid State Circuits 53 (3) (2018)
Satoshi Matsubara, Hirotaka Tamura, Motomu Takatsu, Danny Yoo, Behraz Vatankhahghadim, Hironobu Yamasaki, Toshiyuki Miyazawa, Sanroku Tsukamoto, Yasuhiro Watanabe, Kazuya Takemoto, Ali Sheikholeslami
Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine. CISIS (2017)
Ali Sheikholeslami
Tutorials. ISSCC (2017)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
Jitter injection for on-chip jitter measurement in PI-based CDRs. CICC (2017)
Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS. IEEE J. Solid State Circuits 52 (12) (2017)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. ISSCC (2017)
Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. ISSCC (2017)
Sayeh Sharifymoghaddam, Ali Sheikholeslami
Low-Swing Signaling for FPGA Power Reduction (Abstract Only). FPGA (2016)
Aynaz Vatankhahghadim, Ali Sheikholeslami
A Multi-level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction. ISMVL (2015)
Aynaz Vatankhahghadim, W. Song, Ali Sheikholeslami
A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA. IEEE Trans. Circuits Syst. II Express Briefs (6) (2015)
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. IEEE J. Solid State Circuits 50 (4) (2015)
Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A Reference-Less Single-Loop Half-Rate Binary CDR. IEEE J. Solid State Circuits 50 (9) (2015)
Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A 3x blind ADC-based CDR for a 20 dB loss channel. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2015)
Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset". IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE. CICC (2014)
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs. VLSIC (2014)
Aynaz Vatankhahghadim, Safeen Huda, Ali Sheikholeslami
A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Yunzhi Dong, Richard Schreier, Wenhua Yang, Sudhir Korrapati, Ali Sheikholeslami
29.2 A 235mW CT 0-3 MASH ADC achieving -167dBFS/Hz NSD with 53MHz BW. ISSCC (2014)
Yunzhi Dong, William Yang, Richard Schreier, Ali Sheikholeslami, Sudhir Korrapati
A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS. IEEE J. Solid State Circuits 49 (12) (2014)
Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A Blind Baud-Rate ADC-Based CDR. IEEE J. Solid State Circuits 48 (12) (2013)
Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. CICC (2013)
Safeen Huda, Ali Sheikholeslami
A Novel STT-MRAM Cell With Disturbance-Free Read Operation. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2013)
Ali Sheikholeslami, Hirotaka Tamura
Design metrics for blind ADC-based wireline receivers. CICC (2013)
Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A blind baud-rate ADC-based CDR. ISSCC (2013)
Ken Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John T. Stonick, Hisakatsu Yamaguchi
10-40 Gb/s I/O design for data communications. ISSCC (2012)
Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS. ISSCC (2011)
Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS. IEEE J. Solid State Circuits 46 (12) (2011)
Ali Sheikholeslami, Franz Dielacher, Miki Moyal, Jafar Savoj, John T. Stonick, Takuji Yamamoto
High-speed transceivers: Standards, challenges, and future. ISSCC (2011)
Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
A pattern-guided adaptive equalizer in 65nm CMOS. ISSCC (2011)
Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS. ISSCC (2011)
Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto
A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. ISSCC (2010)
Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. IEEE J. Solid State Circuits 45 (6) (2010)
David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki
Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. ISSCC (2010)
Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers. CICC (2010)
Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC (2010)
Ali Sheikholeslami, Robert Payne
Will ADCs overtake binary frontends in backplane signaling? ISSCC (2009)
Khalil Gorgani Firouzjah, Ali Sheikholeslami
A current independent method based on synchronized voltage measurement for fault location on transmission lines. Simul. Model. Pract. Theory 17 (4) (2009)
Khalil Gorgani Firouzjah, Ali Sheikholeslami, Mohammad Reza Karami Mollaei, F. Heydari
A predictive current control method for shunt active filter with windowing based wavelet transform in harmonic detection. Simul. Model. Pract. Theory 17 (5) (2009)
Ali Sheikholeslami
Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial). ISMVL (2009)
Oleksiy Tyshchenko, Ali Sheikholeslami
Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM). IEEE J. Solid State Circuits 43 (9) (2008)
Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2008)
David Halupka, Alireza Seyed Rabi, Parham Aarabi, Ali Sheikholeslami
Low-Power Dual-Microphone Speech Enhancement Using Field Programmable Gate Arrays. IEEE Trans. Signal Process. 55 (7-1) (2007)
Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. IEEE J. Solid State Circuits 42 (10) (2007)
Ricky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers. CICC (2006)
Duy Cuong Nguyen, David Halupka, Parham Aarabi, Ali Sheikholeslami
Real-time face detection and lip feature extraction using field-programmable gate arrays. IEEE Trans. Syst. Man Cybern. Part B 36 (4) (2006)
Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Shoichi Masui, Kenji Mukaida
An area-efficient universal cryptography processor for smart cards. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Kostas Pagiamtzis, Ali Sheikholeslami
Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE J. Solid State Circuits 41 (3) (2006)
Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
A 3.2Gb/s Semi-Blind-Oversampling CDR. ISSCC (2006)
David Halupka, Alireza Seyed Rabi, Parham Aarabi, Ali Sheikholeslami
Real-time dual-microphone speech enhancement using field programmable gate arrays. ICASSP (5) (2005)
David Halupka, Nebu John Mathai, Parham Aarabi, Ali Sheikholeslami
Robust sound localization in 0.18 µm CMOS. IEEE Trans. Signal Process. 53 (6) (2005)
Kostas Pagiamtzis, Ali Sheikholeslami
Using cache to reduce power in content-addressable memories (CAMs). CICC (2005)
Yadollah Eslami, Ali Sheikholeslami, Shoichi Masui, Toru Endo, Shoichiro Kawashima
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM). IEEE J. Solid State Circuits 39 (11) (2004)
Marcus van Ierssel, Joyce Wong, Ali Sheikholeslami
An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling. SoCC (2004)
Kostas Pagiamtzis, Ali Sheikholeslami
A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme. IEEE J. Solid State Circuits 39 (9) (2004)
Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu
A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL (2004)
Duy Cuong Nguyen, Parham Aarabi, Ali Sheikholeslami
Real-time sound localization using field-programmable gate arrays. ICME (2003)
Igor Arsovski, Trevis Chandler, Ali Sheikholeslami
A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme. IEEE J. Solid State Circuits 38 (1) (2003)
Duy Cuong Nguyen, Parham Aarabi, Ali Sheikholeslami
Real-time sound localization using field-programmable gate arrays. ICASSP (2) (2003)
Nebu John Muthui, Ali Sheikholeslami, Deepa Kundur
VLSI implementation of a real-time video watermark embedder and detector. ISCAS (2) (2003)
Simon Segars, Ali Sheikholeslami, Stephen Fischer
Guest editorial [Special issue of the digital, memory, and signal processing sessions of the 2003 ISSCC]. IEEE J. Solid State Circuits 38 (11) (2003)
Ali Sheikholeslami, D. Michael Miller
Introduction: Special Issue in Recognition of Kenneth C. Smith. J. Multiple Valued Log. Soft Comput. 9 (1) (2003)
Igor Arsovski, Ali Sheikholeslami
A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories. IEEE J. Solid State Circuits 38 (11) (2003)
Marcus van Ierssel, Tooraj Esmailian, Ali Sheikholeslami, P. S. Pasupathy
Signaling capacity of FR4 PCB traces for chip-to-chip communication. ISCAS (5) (2003)
Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories. IEEE J. Solid State Circuits 38 (3) (2003)
Kostas Pagiamtzis, Ali Sheikholeslami
Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories. CICC (2003)
Nebu John Mathai, Deepa Kundur, Ali Sheikholeslami
Hardware implementation perspectives of digital video watermarking algorithms. IEEE Trans. Signal Process. 51 (4) (2003)
Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima
A 16 kb 1T1C FeRAM test chip using current-based reference scheme. CICC (2002)
Ali Sheikholeslami, P. Glenn Gulak
A survey of circuit innovations in ferroelectric random-access memories. Proc. IEEE 88 (5) (2000)
Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak
Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic. ISMVL (1998)
Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu
A Multiple-Valued Ferroelectric Content-Addressable Memory. ISMVL (1996)