D. Michael Miller

Publication Activity (10 Years)

Years Active: 1976-2021
Publications (10 Years): 13

Top Topics

Logic Synthesis

Prime Implicants

Quantum Computing

Top Venues

J. Multiple Valued Log. Soft Comput.

Publications

D. Michael Miller, Gerhard W. Dueck
Function translations and search-based transformation for MVL reversible circuit synthesis. Sci. Comput. Program. 212 (2021)
D. Michael Miller, Gerhard W. Dueck
Descending Order Transformation-based Synthesis of MVL Reversible Circuits. ISMVL (2021)
Kaitlin N. Smith, Mitchell A. Thornton, D. Michael Miller
Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal Transforms. ISMVL (2020)
D. Michael Miller, Gerhard W. Dueck
Search-Based Transformation Synthesis for 3-Valued Reversible Circuits. RC (2020)
D. Michael Miller, Mathias Soeken
A Spectral Algorithm for 3-valued Function Equivalence Classification. J. Multiple Valued Log. Soft Comput. 34 (3-4) (2020)
Mathias Soeken, Eleonora Testa, D. Michael Miller
A Hybrid Method for Spectral Translation Equivalent Boolean Functions. PACRIM (2019)
D. Michael Miller, Mathias Soeken
A Spectral Algorithm for Ternary Function Classification. ISMVL (2018)
Chikatoshi Yamada, D. Michael Miller
Using SPIN to Check Simulink Stateflow Models. Int. J. Networked Distributed Comput. 4 (1) (2016)
Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller
An extension of transformation-based reversible and quantum circuit synthesis. ISCAS (2016)
Chikatoshi Yamada, D. Michael Miller
Using SPIN to Check Simulink Stateflow Models. Int. J. Networked Distributed Comput. 4 (3) (2016)
Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Embedding of Large Boolean Functions for Reversible Logic. ACM J. Emerg. Technol. Comput. Syst. 12 (4) (2016)
Mathias Soeken, Gerhard W. Dueck, D. Michael Miller
A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. RC (2016)
Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler
QMDDs: Efficient Quantum Function Representation and Manipulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (1) (2016)
Radomir S. Stankovic, D. Michael Miller
Using QMDD in Numerical Methods for Solving Linear Differential Equations via Walsh Functions. ISMVL (2015)
Chikatoshi Yamada, D. Michael Miller
Using SPIN to Check Nondeterministic Simulink Stateflow Models. ISMVL (2015)
Chikatoshi Yamada, D. Michael Miller
Using SPIN to check Simulink Stateflow models. ICIS (2015)
Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
Self-Inverse Functions and Palindromic Circuits. CoRR (2015)
Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
Trading off circuit lines and gate costs in the synthesis of reversible logic. Integr. 47 (2) (2014)
Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller
Reversible, Information-Preserving Logic and Its Application. J. Multiple Valued Log. Soft Comput. 23 (3-4) (2014)
Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Embedding of Large Boolean Functions for Reversible Logic. CoRR (2014)
D. Michael Miller, Mathias Soeken, Rolf Drechsler
Mapping NCV Circuits to Optimized Clifford+T Circuits. RC (2014)
Mathias Soeken, D. Michael Miller, Rolf Drechsler
On quantum circuits employing roots of the Pauli matrices. CoRR (2013)
Zahra Sasanian, Robert Wille, D. Michael Miller
Clarification on the Mapping of Reversible Circuits to the NCV-v1 Library. CoRR (2013)
D. Michael Miller, Zahra Sasanian
Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries. ISED (2012)
Zahra Sasanian, Robert Wille, D. Michael Miller
Realizing reversible circuits using a new class of quantum gates. DAC (2012)
Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
Synthesis of Semi-Classical Quantum Circuits. J. Multiple Valued Log. Soft Comput. 18 (1) (2012)
Zahra Sasanian, D. Michael Miller
Reversible and Quantum Circuit Optimization: A Functional Approach. RC (2012)
Zahra Sasanian, D. Michael Miller
Mapping a Multiple-control Toffoli Gate Cascade to an Elementary Quantum Gate Circuit. J. Multiple Valued Log. Soft Comput. 18 (1) (2012)
Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL (2012)
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Equivalence Checking of Reversible Circuits. J. Multiple Valued Log. Soft Comput. 19 (4) (2012)
Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski
High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation? J. Multiple Valued Log. Soft Comput. 20 (1-2) (2012)
D. Michael Miller, Robert Wille, Rolf Drechsler
Reducing Reversible Circuit Cost by Adding Lines. J. Multiple Valued Log. Soft Comput. 19 (1-3) (2012)
Zahra Sasanian, D. Michael Miller
Transforming MCT Circuits to NCVW Circuits. RC (2011)
Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller
Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation. ISMVL (2011)
D. Michael Miller, Robert Wille, Zahra Sasanian
Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates. ISMVL (2011)
Stanislav Stankovic, Jaakko Astola, D. Michael Miller, Radomir S. Stankovic
Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian Groups. ISMVL (2010)
D. Michael Miller, Robert Wille, Rolf Drechsler
Reducing Reversible Circuit Cost by Adding Lines. ISMVL (2010)
David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller
Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics. J. Multiple Valued Log. Soft Comput. 15 (4) (2009)
D. Michael Miller, Robert Wille, Gerhard W. Dueck
Synthesizing Reversible Circuits for Irreversible Functions. DSD (2009)
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Equivalence Checking of Reversible Circuits. MBMV (2009)
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Equivalence Checking of Reversible Circuits. ISMVL (2009)
D. Michael Miller, Radomir S. Stankovic
A Heterogeneous Decision Diagram Package. EUROCAST (2009)
Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
An efficient verification of quantum circuits under a practical restriction. CIT (2008)
Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller
Quantum Logic Implementation of Unary Arithmetic Operations. ISMVL (2008)
David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. DATE (2008)
Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne
Quantum Circuit Simplification and Level Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller
On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. ISMVL (2008)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12 (4) (2007)
D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton
Variable Reordering and Sifting for QMDD. ISMVL (2007)
Dmitri Maslov, D. Michael Miller
Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits. IET Comput. Digit. Tech. 1 (2) (2007)
D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton
QMDD Minimization Using Sifting for Variable Reordering. J. Multiple Valued Log. Soft Comput. 13 (4-6) (2007)
D. Michael Miller, Mitchell A. Thornton
QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. ISMVL (2006)
D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
Synthesis of Quantum Multiple-Valued Circuits. J. Multiple Valued Log. Soft Comput. 12 (5-6) (2006)
D. Michael Miller, Mitchell A. Thornton, David Goodman
A Decision Diagram Package for Reversible and Quantum Circuit Simulation. IEEE Congress on Evolutionary Computation (2006)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. Very Large Scale Integr. Syst. 13 (6) (2005)
Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck
Quantum Circuit Simplification Using Templates. DATE (2005)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Toffoli network synthesis with templates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (6) (2005)
Mitchell A. Thornton, D. Michael Miller
Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs. J. Multiple Valued Log. Soft Comput. 10 (2) (2004)
D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov
A Synthesis Method for MVL Reversible Logi. ISMVL (2004)
D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
A transformation based algorithm for reversible logic synthesis. DAC (2003)
Ali Sheikholeslami, D. Michael Miller
Introduction: Special Issue in Recognition of Kenneth C. Smith. J. Multiple Valued Log. Soft Comput. 9 (1) (2003)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD (2003)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Simplification of Toffoli Networks via Templates. SBCCI (2003)
D. Michael Miller, Rolf Drechsler
Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL (2003)
D. Michael Miller, Gerhard W. Dueck
On the Size of Multiple-Valued Decision Diagrams. ISMVL (2003)
D. Michael Miller, Rolf Drechsler
On the Construction of Multiple-Valued Decision Diagrams. ISMVL (2002)
Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
Multi-Output Timed Shannon Circuits. ISVLSI (2002)
Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI (2002)
Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend
Chrestenson Spectrum Computation Using Cayley Color Graphs. ISMVL (2002)
Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio
TOP: An Algorithm for Three-Level Optimization of PLDs. DATE (2000)
Yasunori Nagata, D. Michael Miller, Masao Mukaidono
Logic Synthesis of Controllers for B-Ternary Asynchronous Systems. ISMVL (2000)
Yasunori Nagata, D. Michael Miller, Masao Mukaidono
B-ternary Logic Based Asynchronous Micropipeline. ISMVL (1999)
D. Michael Miller, Rolf Drechsler
Implementing a Multiple-Valued Decision Diagram Package. ISMVL (1998)
Yasunori Nagata, D. Michael Miller, Masao Mukaidono
Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs. ISMVL (1998)
D. Michael Miller
An improved method for computing a generalized spectral coefficient. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (3) (1998)
D. Michael Miller
A spectral method for Boolean function matching. ED&TC (1996)
D. Michael Miller, Noriaki Muranaka
Multiple-Valued Decision Diagrams with Symmetric Variable Nodes. ISMVL (1996)
Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller
A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. ISMVL (1996)
Shujian Zhang, D. Michael Miller, Jon C. Muzio
Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller
Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. J. Electron. Test. 7 (3) (1995)
D. Michael Miller
Spectral Transformation of Multiple-Valued Decision Diagrams. ISMVL (1994)
Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller
Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults. ISCAS (1994)
Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller
-Valued Decimal Signed-Digit Number Representation. ISMVL (1993)
D. Michael Miller
Multiple-Valued Logic Design Tools. ISMVL (1993)
D. M. Marcynuk, D. Michael Miller
The OR-k method for on-line checking of programmable logic arrays. J. Electron. Test. 3 (1) (1992)
Shujian Zhang, Rod Byrne, D. Michael Miller
BIST Generators for Sequential Faults. ICCD (1992)
R. Tomczuk, D. Michael Miller
Autocorrelation Techniques for Multi-Bit Decoder PLAs. ISMVL (1992)
D. Michael Miller, Shujian Zhang, Werner Pries, Robert D. McLeod
Estimating aliasing in CA and LFSR based signature registers. ICCD (1990)
Gerhard W. Dueck, D. Michael Miller
RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL (1990)
Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller
The analysis of one-dimensional linear cellular automata and their aliasing properties. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (7) (1990)
Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. Michael Miller, Howard C. Card
Cellular automata-based pseudorandom number generators for built-in self-test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (8) (1989)
D. Michael Miller, Jon C. Muzio
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks. IEEE Trans. Computers 33 (8) (1984)
D. Michael Miller, Jon C. Muzio
Spectral Fault Signatures for Internally Unate Combinational Networks. IEEE Trans. Computers 32 (11) (1983)
D. Michael Miller, Jon C. Muzio
A class of two-place three-valued unary generators. Notre Dame J. Formal Log. 21 (1) (1980)
D. Michael Miller, Jon C. Muzio
A ternary universal decision element. Notre Dame J. Formal Log. 17 (4) (1976)