A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs.

Noriaki Muranaka Shigenobu Arai Shigeru Imanishi D. Michael Miller

Published in: ISMVL (1996)

Keyphrases

low voltage
neural network
life cycle
high speed
flip flops
product quality
circuit design
digital circuits
objective function
product design
design considerations
square error
data sets
np hard
learning algorithm
production planning
frequency response
genetic algorithm
electronic circuits