Joshua Liang

Publication Activity (10 Years)

Years Active: 2010-2022
Publications (10 Years): 8

Top Topics

Design Considerations

Delay Insensitive

Analog To Digital Converter

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yi Fan Zhang, Joshua Liang, Tony Chan Carusone
Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators. ISCAS (2022)
Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC (2019)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs. IEEE J. Solid State Circuits 53 (9) (2018)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR. IEEE J. Solid State Circuits 53 (3) (2018)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
Jitter injection for on-chip jitter measurement in PI-based CDRs. CICC (2017)
Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS. IEEE J. Solid State Circuits 52 (12) (2017)
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. ISSCC (2017)
Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. ISSCC (2017)
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. IEEE J. Solid State Circuits 50 (4) (2015)
Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A 3x blind ADC-based CDR for a 20 dB loss channel. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2015)
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs. VLSIC (2014)
Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A Blind Baud-Rate ADC-Based CDR. IEEE J. Solid State Circuits 48 (12) (2013)
Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A blind baud-rate ADC-based CDR. ISSCC (2013)
Joshua Liang, David A. Johns
A frequency-scalable 15-bit incremental ADC for low power sensor applications. ISCAS (2010)