Mohammad Sadegh Jalali

Publication Activity (10 Years)

Years Active: 2010-2018
Publications (10 Years): 5

Top Topics

Motion Deblurring

Measurement Error

Phase Difference

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

Publications

Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support. ISSCC (2018)
Mohammad Sadegh Jalali, Masum Hossain, Kenneth Dyer, Saman Sadr
High speed ADCs for wireline applications. MWSCAS (2017)
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. IEEE J. Solid State Circuits 50 (4) (2015)
Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A Reference-Less Single-Loop Half-Rate Binary CDR. IEEE J. Solid State Circuits 50 (9) (2015)
Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A 3x blind ADC-based CDR for a 20 dB loss channel. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2015)
Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset". IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE. CICC (2014)
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs. VLSIC (2014)
Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. CICC (2013)
Mohammad Sadegh Jalali, Alireza Sharif Bakhtiar, Shahriar Mirabbasi
A hybrid phase-locked loop for CDR Applications. ISCAS (2011)
Alireza Sharif Bakhtiar, Mohammad Sadegh Jalali, Shahriar Mirabbasi
An RF power harvesting system with input-tuning for long-range RFID tags. ISCAS (2010)