Shayan Shahramian

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 6

Top Topics

Infinite Impulse Response

Reinforcement Learning

Adaptation Process

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Cameron Haigh, Zichen Zhang, Negar Hassanpour, Khurram Javed, Yingying Fu, Shayan Shahramian, Shawn Zhang, Jun Luo
Drawing Inductor Layout with a Reinforcement Learning Agent: Method and Application for VCO Inductors. CoRR (2022)
Ming Yang, Shayan Shahramian, Henry Wong, Peter Krotnev, Anthony Chan Carusone
Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. ISCAS (2021)
Ming Yang, Shayan Shahramian, Hossein Shakiba, Henry Wong, Peter Krotnev, Anthony Chan Carusone
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC (2019)
Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs. IEEE J. Solid State Circuits 51 (12) (2016)
Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs. ISSCC (2016)
Shayan Shahramian, Anthony Chan Carusone
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS". IEEE J. Solid State Circuits 50 (10) (2015)
Shayan Shahramian, Anthony Chan Carusone
A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS. IEEE J. Solid State Circuits 50 (7) (2015)
Shayan Shahramian, Anthony Chan Carusone
A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS. ESSCIRC (2014)
Shayan Shahramian, Hemesh Yasotharan, Anthony Chan Carusone
Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters. IEEE Trans. Circuits Syst. II Express Briefs (6) (2012)
Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
A pattern-guided adaptive equalizer in 65nm CMOS. ISSCC (2011)