A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS.
Shayan ShahramianAnthony Chan CarusonePublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- high speed
- nm technology
- linear programming
- random access memory
- low power
- linear program
- power consumption
- cmos technology
- optimal solution
- silicon on insulator
- markov chain
- analog vlsi
- receding horizon
- analog to digital converter
- low cost
- real time
- circuit design
- finite state
- metal oxide semiconductor
- objective function