David Cassan

Publication Activity (10 Years)

Years Active: 2002-2022
Publications (10 Years): 3

Top Topics

Decision Feedback

Wireless Transmission

Top Venues

IEEE J. Solid State Circuits

Publications

James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan, Davide Tonietto
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. IEEE J. Solid State Circuits 57 (1) (2022)
James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. ISSCC (2021)
Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC (2019)
Chris D. Holdenried, Ryan Bespalko, Marcus van Ierssel, Mehrdad Ramezani, David Cassan, Siamak Sarvari, Saman Sadr
Performance of edge tap decision feedback equalization methods for wireline receivers. NEWCAS (2014)
Kamran Farzan, Mehrdad Ramezani, Angus McLaren, Roman Pahuta, Nadeesha Amarasinghe, David Cassan, Saman Sadr
A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology. ESSCIRC (2012)
Mehrdad Ramezani, Mohamed Abdalla, Ayal Shoval, Marcus van Ierssel, Afshin Rezayee, Angus McLaren, Chris D. Holdenried, Jennifer Pham, Eric So, David Cassan, Saman Sadr
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology. ISSCC (2011)
David Cassan, John R. Long
A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS. IEEE J. Solid State Circuits 38 (3) (2003)
David Cassan, John R. Long
A 1 V 0.9 dB NF low noise amplifier for 5-6 GHz WLAN in 0.18 μm CMOS. CICC (2002)