Marc-Andre LaCroix

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 8

Top Topics

Power Reduction

Wireless Transmission

Adaptive Threshold

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Dirk Pfaff, Muhammad Nummer, Noman Hai, Peter Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson Dick, Alif Zaman, Haitao Mei, Shahab Moazzeni, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri
7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS. ISSCC (2024)
James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan, Davide Tonietto
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. IEEE J. Solid State Circuits 57 (1) (2022)
James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. ISSCC (2021)
Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2. ISSCC (2021)
Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone
A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET. IEEE J. Solid State Circuits 54 (2) (2019)
Marc-Andre LaCroix, Henry Wong, Yun Hua Liu, Huong Ho, Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss. ISSCC (2019)
Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone
A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET. ISSCC (2018)
Luke Wang, Marc-Andre LaCroix, Anthony Chan Carusone
A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET. IEEE Trans. Circuits Syst. II Express Briefs (12) (2017)
Paul Madeira, Marc-Andre LaCroix, John Hogeboom
A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology. ESSCIRC (2007)