A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology.

Paul Madeira Marc-Andre LaCroix John Hogeboom

Published in: ESSCIRC (2007)

Keyphrases

cmos technology
low power
power dissipation
image sensor
high speed
power consumption
spl times
low voltage
parallel processing
low cost
silicon on insulator
circuit design
mixed signal
dynamic range
video camera
random access memory
embedded dram
image processing