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A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver.

James BaileyHossein ShakibaEhud NirGrigory MarderfeldPeter KrotnevMarc-Andre LaCroixDavid Cassan
Published in: ISSCC (2021)
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