A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver.
James BaileyHossein ShakibaEhud NirGrigory MarderfeldPeter KrotnevMarc-Andre LaCroixDavid CassanPublished in: ISSCC (2021)
Keyphrases
- low power
- high speed
- decision feedback
- cmos technology
- power consumption
- low cost
- nm technology
- single chip
- multipath
- high power
- error propagation
- vlsi circuits
- wireless transmission
- mixed signal
- power reduction
- vlsi architecture
- low power consumption
- delay insensitive
- ultra low power
- wireless networks
- low voltage
- digital signal processing
- image sensor
- power saving
- signal processing
- power dissipation
- real time
- gate array
- computer simulation